https://riscv.org/2019/02/adacore-enhances-security-critical-firmware-with-nvidia/
To me, a programming language is roughly a function from strings to behaviors---a function from source to expected result. Specifically, it says nothing about the implementation, only how it can be used.
There is some sense in which an ISA is exactly that---it does not specify implementation, only how it can be used, and the expected behavior that should arise. However, ISA's do not specify a function from strings to behaviors like normal programming languages. As such, there are usually multiple assembler syntaxes for a single ISA.
What are your thoughts? Is the class ISA a subclass of ProgrammingLanguage? Or are they somehow separate?
TL;DR
I'm reading up on the RISC-V specs, but I'm not sure how to implement the hardware. And I have no idea at all how to load software onto it.
\TL;DR
I'm reading the RISC-V user-level ISA spec sheet, as well as Patterson's book providing an overview of how the instruction set works.
There are a few things that I don't quite get about the ISA itself just yet, but that's not the point of this post.
The point of this post is that I don't know how to do, well, everything else.
For starters, are there any guidelines for how to implement the rest of the processor? The ISA spec basically tells me only how to decode the instructions and prepare them for execution, if I'm not mistaken. That leaves things like pipeline depth, branch prediction, caching, the actual execution hardware, and the overall hardware layout up to the designer, right? In which case, are there any guidelines as to how I should set those things up? I suppose I can compare results after running some benchmark, but that kinda leads me to a further problem when it comes to loading a program.
Let's say I successfully write up a synthesizable VHDL model of the core and I want to load the bitstream onto my Arty S7 FPGA board. First of all, for instruction and data memory, I want to use the off-chip DDR3L RAM instead of the block RAM, right? Would the IP block RAM be suitable for a cache, or do I want to use flip-flops? Or both, with different hardware for L1 and L2 caches?
Then comes the challenge of loading a program to run on the core. I suppose I can fumble my way through writing a crude assembler program or script to translate assembly instructions into binary lines. And then, I guess I need some kind of program loader logic on my board (which may be available as an IP core) to interface between the UART and the DDR3L. And then I can use a terminal program to stream the binaries to the UART to load the program memory.
But what if I want to compile C code to target the RISC-V platform? I don't know anything about toolchains. I've only ever programmed microcontrollers in integrated development environments; I know how to write code and click "compile" and "run". I don't really understand anything about GCC or Make or anything like that. Are there options to do that sort of stuff on a Windows machine, or is it all Linux stuff? Should I look for an Eclipse or Visual Studio plugin to
... keep reading on reddit ➡With Intel cancelling their 10nm chips, I've seen alot of comments talking about "core architecture" for intel and "zen architecture" for AMD. I think I understand that architecture is how individual processors handle instructions, if that's right. Don't both of these chips run on the x86 instruction set? Doesn't that mean they have the same architecture? In another thread, I saw someone mention that intel may have bribed companies to use a compiler that favored intel's core architecture, but if they both use the same x86 instruction set, how is this possible?
I also think that I understand that a node is an individual transistor/gate/etc combo, basically the smallest functional unit in a processor. Is it true that a intel's 10nm "process" was the manufacturing process by which they hoped to create a chip that contained (x)billion 10nm nodes (transistors), or that TSMC's 7nm process is the manufacturing setup to produce their 7nm chips that AMD will use? Is the "process" the method they use to cut the silicon from wafers?
I think many people use some of these words interchangeably when, in fact, they aren't interchangeable, which has confused me. Can anyone help me understand?
In this paper, researchers at Rigetti computing create an instruction set architecture for hybrid classical/quantum computers.
Link to paper: https://arxiv.org/pdf/1608.03355.pdf
Questions and comments welcome.
While I am aware that AMD invented and currently uses the x86-64 instruction set, if RISC-V or similar proves to have higher performance and efficiency, would they adopt it anyway? Would RISC-V gain more software support as a result?
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Citation: John R. Ellis. 1985. Bulldog: A Compiler for Vliw Architectures (Parallel Computing, Reduced-Instruction-Set, Trace Scheduling, Scientific). Ph.D. Dissertation. Yale University, New Haven, CT, USA. AAI8600982.
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DOI/PMID/ISBN: http://hdl.handle.net/10079/bibid/9853167
