Whats the difference between architecture and instruction set?
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πŸ‘€︎ u/sirwaffleburger
πŸ“…︎ Nov 27 2020
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Some NVIDIA system-on-a-chip product lines will migrate to a new architecture using the RISC-V Instruction Set Architecture (ISA)

https://riscv.org/2019/02/adacore-enhances-security-critical-firmware-with-nvidia/

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πŸ‘€︎ u/dylan522p
πŸ“…︎ Jul 01 2019
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Mecrisp-Quintus is a rewrite of classic Mecrisp-Stellaris with almost the same look-and-feel for RISC-V architecture, RV32IM flavour. It runs on the HiFive1, on PicoRV by Clifford Wolf for HX8K FPGA and with the help of Mamihlapinatapai, a special instruction set emulator, on two ARM targets [...] mecrisp.sourceforge.net/
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πŸ‘€︎ u/eleitl
πŸ“…︎ Feb 04 2020
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IBM POWER Instruction Set Architecture Now Open Source infoq.com/news/2019/08/ib…
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πŸ‘€︎ u/thatsocrates
πŸ“…︎ Aug 28 2019
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A Complete Formal Semantics of x86-64 User-Level Instruction Set Architecture fsl.cs.illinois.edu/index…
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πŸ‘€︎ u/mttd
πŸ“…︎ Apr 23 2019
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"Great Instruction Set Architectures" Reading Seminar cs.cornell.edu/courses/cs…
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πŸ‘€︎ u/mttd
πŸ“…︎ Jan 21 2020
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"Vega" 7nm Instruction Set Architecture: (Published: Nov 26, 2019) gpuopen.com/wp-content/up…
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πŸ‘€︎ u/dragontamer5788
πŸ“…︎ Dec 15 2019
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IBM Demonstrates Commitment to Open Hardware Movement. IBM is opening the POWER Instruction Set Architecture (ISA). newsroom.ibm.com/2019-08-…
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πŸ‘€︎ u/JohnDoe_John
πŸ“…︎ Aug 21 2019
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The Lexra Story: cloning the MIPS-I instruction set architecture 1997-2003. probell.com/lexra/
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πŸ‘€︎ u/pdp10
πŸ“…︎ Sep 23 2019
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ARM Launches "Facts" Campaign Against RISC-V (open-source processor instruction set architecture) phoronix.com/scan.php?pag…
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πŸ‘€︎ u/br_shadow
πŸ“…︎ Jul 09 2018
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The RISC V Instruction Set Architecture Explained devtechnica.com/computer-…
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πŸ‘€︎ u/sreedev97
πŸ“…︎ Feb 11 2019
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Design of the RISC-V Instruction Set Architecture [pdf] eecs.berkeley.edu/~waterm…
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πŸ‘€︎ u/johnmountain
πŸ“…︎ May 01 2016
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Are instruction set architectures programming languages? Why or why not?

To me, a programming language is roughly a function from strings to behaviors---a function from source to expected result. Specifically, it says nothing about the implementation, only how it can be used.

There is some sense in which an ISA is exactly that---it does not specify implementation, only how it can be used, and the expected behavior that should arise. However, ISA's do not specify a function from strings to behaviors like normal programming languages. As such, there are usually multiple assembler syntaxes for a single ISA.

What are your thoughts? Is the class ISA a subclass of ProgrammingLanguage? Or are they somehow separate?

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πŸ‘€︎ u/extremeaxe5
πŸ“…︎ May 14 2019
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AMD RDNA 1.0 Instruction Set Architecture - GPUOpen gpuopen.com/compute-produ…
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πŸ‘€︎ u/G4M1NG
πŸ“…︎ Aug 01 2019
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Apple receives patent for processor including multiple dissimilar processor cores that implement different portions of instruction set architecture patft.uspto.gov/netacgi/n…
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πŸ‘€︎ u/dylan522p
πŸ“…︎ May 01 2018
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IBM is open sourcing the Power instruction set architecture nextplatform.com/2019/08/…
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πŸ‘€︎ u/qznc_bot2
πŸ“…︎ Aug 20 2019
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A clueless idiot needs help with implementing the RISC-V instruction set architecture in simulation or hardware. Please assist?

TL;DR

I'm reading up on the RISC-V specs, but I'm not sure how to implement the hardware. And I have no idea at all how to load software onto it.

\TL;DR

I'm reading the RISC-V user-level ISA spec sheet, as well as Patterson's book providing an overview of how the instruction set works.

There are a few things that I don't quite get about the ISA itself just yet, but that's not the point of this post.

The point of this post is that I don't know how to do, well, everything else.

For starters, are there any guidelines for how to implement the rest of the processor? The ISA spec basically tells me only how to decode the instructions and prepare them for execution, if I'm not mistaken. That leaves things like pipeline depth, branch prediction, caching, the actual execution hardware, and the overall hardware layout up to the designer, right? In which case, are there any guidelines as to how I should set those things up? I suppose I can compare results after running some benchmark, but that kinda leads me to a further problem when it comes to loading a program.

Let's say I successfully write up a synthesizable VHDL model of the core and I want to load the bitstream onto my Arty S7 FPGA board. First of all, for instruction and data memory, I want to use the off-chip DDR3L RAM instead of the block RAM, right? Would the IP block RAM be suitable for a cache, or do I want to use flip-flops? Or both, with different hardware for L1 and L2 caches?

Then comes the challenge of loading a program to run on the core. I suppose I can fumble my way through writing a crude assembler program or script to translate assembly instructions into binary lines. And then, I guess I need some kind of program loader logic on my board (which may be available as an IP core) to interface between the UART and the DDR3L. And then I can use a terminal program to stream the binaries to the UART to load the program memory.

But what if I want to compile C code to target the RISC-V platform? I don't know anything about toolchains. I've only ever programmed microcontrollers in integrated development environments; I know how to write code and click "compile" and "run". I don't really understand anything about GCC or Make or anything like that. Are there options to do that sort of stuff on a Windows machine, or is it all Linux stuff? Should I look for an Eclipse or Visual Studio plugin to

... keep reading on reddit ➑

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πŸ“…︎ Sep 21 2018
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Design of the RISC-V Instruction Set Architecture eecs.berkeley.edu/~waterm…
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πŸ‘€︎ u/nickdesaulniers
πŸ“…︎ May 01 2016
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Difference between architecture, instruction set, node, and process?

With Intel cancelling their 10nm chips, I've seen alot of comments talking about "core architecture" for intel and "zen architecture" for AMD. I think I understand that architecture is how individual processors handle instructions, if that's right. Don't both of these chips run on the x86 instruction set? Doesn't that mean they have the same architecture? In another thread, I saw someone mention that intel may have bribed companies to use a compiler that favored intel's core architecture, but if they both use the same x86 instruction set, how is this possible?

I also think that I understand that a node is an individual transistor/gate/etc combo, basically the smallest functional unit in a processor. Is it true that a intel's 10nm "process" was the manufacturing process by which they hoped to create a chip that contained (x)billion 10nm nodes (transistors), or that TSMC's 7nm process is the manufacturing setup to produce their 7nm chips that AMD will use? Is the "process" the method they use to cut the silicon from wafers?

I think many people use some of these words interchangeably when, in fact, they aren't interchangeable, which has confused me. Can anyone help me understand?

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πŸ‘€︎ u/commontatersc2
πŸ“…︎ Oct 22 2018
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A Complete Formal Semantics of x86-64 User-Level Instruction Set Architecture fsl.cs.illinois.edu/index…
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πŸ‘€︎ u/mttd
πŸ“…︎ Apr 23 2019
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An EE Guide to Instruction Set Architectures allaboutcircuits.com/tech…
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πŸ‘€︎ u/hardyhana
πŸ“…︎ Sep 05 2018
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Week 6 Discussion: A Practical Quantum Instruction Set Architecture

In this paper, researchers at Rigetti computing create an instruction set architecture for hybrid classical/quantum computers.

Link to paper: https://arxiv.org/pdf/1608.03355.pdf

Questions and comments welcome.

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πŸ‘€︎ u/vtomole
πŸ“…︎ Aug 01 2017
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ZISC: Zero Instruction Set Computer Architecture kevindowd.com/zisc.txt
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πŸ‘€︎ u/gthank
πŸ“…︎ Jun 07 2013
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Is AMD likely to begin manufacturing processors based on an open-source RISC instruction set architecture such as RISC-V?

While I am aware that AMD invented and currently uses the x86-64 instruction set, if RISC-V or similar proves to have higher performance and efficiency, would they adopt it anyway? Would RISC-V gain more software support as a result?

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πŸ‘€︎ u/Logic_and_Memes
πŸ“…︎ Jul 25 2016
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Formal Specification of the x86 Instruction Set Architecture (Thesis, Ulan Degenbaev) [PDF] rg-master.cs.uni-sb.de/pu…
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πŸ‘€︎ u/igor_sk
πŸ“…︎ Aug 08 2013
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[Thesis] Bulldog: a compiler for vliw architectures (parallel computing, reduced-instruction-set, trace scheduling, scientific)
  • Citation: John R. Ellis. 1985. Bulldog: A Compiler for Vliw Architectures (Parallel Computing, Reduced-Instruction-Set, Trace Scheduling, Scientific). Ph.D. Dissertation. Yale University, New Haven, CT, USA. AAI8600982.

  • DOI/PMID/ISBN: http://hdl.handle.net/10079/bibid/9853167

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πŸ‘€︎ u/soilovin
πŸ“…︎ May 13 2017
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RISC-V ISA - Part 1b - course pre-launched. Here's the link: https://www.udemy.com/vsd-riscv-instruction-set-architecture-isa-part-1b/ youtube.com/attribution_l…
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πŸ‘€︎ u/kunalg123
πŸ“…︎ Dec 08 2017
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Instruction Set Completeness Theorem: Concept, Relevance, Proof, and Example for Processor Architecture gsjournal.net/Science-Jou…
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πŸ‘€︎ u/andygauge
πŸ“…︎ Mar 28 2017
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QUARK is a simple dual-stack CPU instruction set architecture (ISA) that can be extended. QUARK uses Head-and-tail instruction format. github.com/drom/quark
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πŸ‘€︎ u/pointfree
πŸ“…︎ Apr 24 2016
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Analyzing the RISC-V Instruction Set Architecture adapteva.com/andreas-blog…
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πŸ‘€︎ u/eleitl
πŸ“…︎ Mar 23 2015
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Improving the Standard SUBLEQ OISC (One Instruction Set Computer) Architecture techtinkering.com/article…
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πŸ‘€︎ u/impomatic
πŸ“…︎ May 20 2009
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[NO SPOILERS] LEGO - Game of Thrones Westeros Skyline Architecture (more images, where to get instructions and other info in comments)
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πŸ‘€︎ u/MOMAtteo79
πŸ“…︎ Oct 02 2018
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Back to The Future Skyline Architecture - More info, images and instructions in comments
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πŸ‘€︎ u/MOMAtteo79
πŸ“…︎ Nov 27 2018
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A Lego skull I made with only the Lego Architecture Studio. Based on instructions for Skull-A-Day by Noah Scanlin. [instructions in comments]
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πŸ‘€︎ u/eric_ravenstein
πŸ“…︎ Feb 24 2020
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Star Wars Skyline Architecture - Instructions Video Render - More info in comments v.redd.it/tm7103qsymf21
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πŸ‘€︎ u/MOMAtteo79
πŸ“…︎ Feb 10 2019
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Star Wars Skyline Architecture - Link to instructions, more info and images in comments
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πŸ‘€︎ u/MOMAtteo79
πŸ“…︎ Nov 15 2018
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Breaking Bad Skyline Architecture MOC - Link to Instructions, more images and info in comments
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πŸ‘€︎ u/MOMAtteo79
πŸ“…︎ Dec 14 2018
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