always @(posedge clk_50MHz) A <= (A > 10) ? 1'b1 : 1'b0;
always @(posedge clk_350MHz)
begin
B <= A;
D <= ~B && A;
end
Both clk_50MHz and clk_350MHz are generated from the same PLL and have the same phase shift.
Would the code snippet above generate any issues such as metastability, etc ?
I have slow asyncronous signal on one of my fpga inputs, that need debouncing. And i have code that handles this issue:
logic [31:0] debounceCount;
localparam updatePer = freq/10;
always @(posedge clk) begin
if (in^out) debounceCount <= debounceCount-1;
else debounceCount <= updatePer;
if (~|debounceCount) out <= in;
end
Should i add syncronizer logic to evade metastability on signal "in" or code i have will be enough?
I'm new to verilog, and I'm essentially teaching myself as I put together this proof of concept for a work project (sole designer, we usually operate in the mcu space but needed a cpld for regulatory reasons here). Short summary is the device is waiting for a dropped signal (nOutageDetect = 0) and will trigger a pair of relays to open and close after a 5s delay. when the signal returns (nOutageDetect = 1) the relays should switch after another 5s delay.
The TB waveform shows that this is happening exactly as designed, but when I try to reproduce it on my prototype test bed the delay stretches out to minutes.
source code:
`timescale 1ps/1ps
module prototype
(relayPos, nOutageDetect, capGood, openRelay, shutRelay, xferSwitch, plugType, manualOverride, LED_utilityPower, LED_dcMonitor, LED_0, LED_1, LED_2, gclk);
input wire relayPos; // 0 = relay closed 1 = relay open
input wire nOutageDetect; // 0 = signal lost 1 = normal
input wire capGood; // 0 = not charged 1 = charged >14v
input wire plugType; // 0 = add-on missing 1 = add-on connected
input wire gclk;
input wire manualOverride;
output reg LED_utilityPower = 1;
output reg LED_dcMonitor = 0;
output reg xferSwitch; // switches secondary relay
output LED_0, LED_1, LED_2; // LEDs programmed for demo debugging. utility likely to change
output reg openRelay = 0; // trigger to open primary relay
output reg shutRelay = 0; // trigger to shut primary relay
//pragma attribute LED_dcMonitor pinnum 4
//pragma attribute LED_utilityPower pinnum 6
//pragma attribute LED_dcOverride pinnum 9
//pragma attribute manualOverride pinnum 40
//pragma attribute plugType pinnum 5
//pragma attribute xferMonitor pinnum 8
//pragma attribute nOutageDetect pinnum 20
//pragma attribute capGood pinnum 34
//pragma attribute relayPos pinnum 11
//pragma attribute shutRelay pinnum 16
//pragma attribute openRelay pinnum 14
//pragma attribute xferSwitch pinnum 39
//pragma attribute gclk pinnum 43
//pragma attribute LED_0 pinnum 12
//pragma attribute LED_1 pinnum 17
//pragma attribute LED_2 pinnum 18
wire [2:0] LED;
assign {LED_2, LED_1, LED_0} = LED;
//////////////////////////////////////////////////
//
// clocking block - 32kHz
I'm just an aficionado so try to keep it dumbed down please!
All articles I've seen state that the mass of the Higgs and the top quark seem to be on the limit between stability and metastability, although it still hasn't been confirmed. My question is not regarding in which state the universe is but why does this measurements relate to it. Why does it mean than if the masses of these particles was different then the universe will be in another estate of stability/instability/metaestability/non-perturbability?
In short, where do the regions of this chart come from and why are they there?
Also, what does the non-perturbability region mean?
Thanks!
EDIT: I see lots of shadow banned people here.
This is an interesting new post on iota.cafe about the Multiverse proposal and its viability 🦾
In life where the only constant thing is change, will you prefer to stick in one place or let yourself be carried away? What pushes you to move forward? In what direction do you want to be lead on?
Eme lang, pa-deep ang lola nyo. Lezz chat naman. Kasabawan talks lamang.
I had always thought this was safe, but now reading this classic Cummings Sunburst paper on metastability, I'm getting paranoid.
I have clk_source = 100 MHz, clk_destination = 200 MHz. Clocks are not synchronous to each other. Both are 50/50 duty cycle. Assume rising edge captured flops only.
Say I have a pulse signal generated in clk_source domain that is 1 cycle wide, so 10ns wide. Pulses are not back to back and instead spread out from each other by say 20 cycles.
Shouldn't I be able to use a "double flop synchronizer" that is clocked in clk_destination domain to reliably guarantee capture of these pulses to this domain?
The clock is twice the frequency and I thought this satisfied some Nyquist rate. Drawing it out, I can't see a case where at least one clock edge of the clk_destination would reliably sample the pulse. There isn't a case I see where the pulse would be completely missed. Is there a case in this scenario where the pulse could possibly be missed?
Ignoring any arguments about MTBF not being completely 0 for a double flop synchronizer, as in a correct usage case, the synchronizer will reduce down to some acceptable level like 99.99%.
EDIT: The section causing me to doubt myself is 4.1.1 where it states "input data values must be stable for three destination clock edges."
Hi.
I had a question in understanding how metastability can result in missing a captured pulse. There are multiple ways to capture pulses across domains, but for the sake of this question, just assume I'm edge detecting.
I have a fast clock at 100 MHz that has data pulses separated by a number of fast clock cycles. I want to capture every event of this pulse in an asynchronous slow clock domain of 50 MHz (half speed). The original fast clock pulse is stretched to be 3x wide to ensure after it goes through a double flop synchronizer, it will be sampled at least once in the slow domain.
As long as there is sufficient cycles between assertions of the stretched fast clock pulse, the slow clock domain should capture them all.
However I'm drawing out a cornercase to show how one assumption of "sufficient cycles between assertions" will not hold true and I think can cause missing a pulse.
This picture_A here shows that clock edge 2 when violating setup time when the Din transitions too closely, the latency through the synchronizer is 2 cycles and both original fast clock cycles are replicated in the slow clock domain.
This picture_B here shows that clock edge 2 when violating setup time, now instead the latency through the synchronizer at this point takes 3 cycles. So I "think" this means that since the first flop in the double flop synchronizer goes metastable, it will not resolve in time to correctly capture at clock edge 3 the low sample, despite the fact that the low sample at this point is completely stable.
Is this correct? So when the first flop goes metastable, the next rising clock edge of a stable Din value will not register in some cases?
After watching the last season of RvB, we now know Lopez has more than enough time to reach that state and considering Lopez has show sign of sentient since early on. Lopez had shown more human like nature as the show goes own plus the fact that he's literally older than Chrovos/Genkins himself since he fall into the black hole before him, learn the truth of the universe (and probably already become a god too by the current time), the chance he is not already metastable is nearly 0.
i hope the next season Lopez will truly be meta stable.
Examples:
-Solipsil (2530-50)
-Deep Winter (2541-51)
-Kusanagi (2535-52)
-Kalmiya (2537-52)
Just those four.
Why YSK: Bringing freezing cold electronic devices into your home will cause them to condensate, which also can happen INSIDE the device. Powering them up can potentially damage sensitive electronic circuitry.
Sum
It’s “battery” operated
Say have an external async signal coming straight from an IO pad into a double flop synchronizer. So have:
async input --> D1 --> Q1 --> D2 --> Q2 --> output
where Q2 is the final safe and stable value (let's not bring in MTBF failing here).
If you have 3 total clock cycles, the output of the synchronizer Q2 can resolve to the value you want either in clock cycle 2 or 3. So there is an indeterminism of 1 cycle here.
Is there a way to calculate after the fact based on Q2 how long it took to resolve? I can't use a difference between Q2 and "async input" as async input is unstable.
Note: I'm not trying to synchronize multlple bits passing each through it's own double flop synchronizer.
)
