Hi everyone! First of all, I'm sorry if this post can be a little bit confusing, I'm trying to gather all I have understood so far to make it as clear as possible.

So, I am attending a Logical Networks class, and we started some days ago talking about sequential circuits. Today, our professor introduced us to synchronous and asynchronous circuits, but not in the same way I found online.

He introduced them by saying this: Basically an asynchronous circuit is a circuit that whatever the state and the input (q1,I) you consider, will always end up in a steady state (qn, I), where if you keep I as an input you'll keep staying in the qn state.

And, contrary to this, he told us that synchronous circuits are circuits where not all states and inputs have this property.

So what does that specifically mean? I struggle to understand the concept, as some of the example he gave us for synchronous circuits (one of them was a machine that was able to recognise if there was a 101 sequence in the input) seemed to have the steady state property I talked about before, so I think I might be missing something.

That said, he then explained us that for that reason (not every state with an input I will end up in a steady state) we need an external synching (a clock) and a memory to make a state steady. Why is that? And why don't we need that for asynchronous circuits?

Lastly, he talked about how some of these machines need just an impulse or a longer signal to work (and for example an asynchronous machine cannot recognise a '00' input as it operates when an input changes, so it can only tell that the last input was a (for example) 1 and this one is a 0). How do you tell that?

Hope this was clear, thank you for everyone who chooses to spend their time to help me understand :)

Oh and, don't take my words for something so accurate of what our professor told us, since I am trying to rephrase these things from what i have understood.

I have designed this circuit in Logisim. It isn't quite a D flip-flop as the output will change whenever the clock is high, not just on the clock edge.

Anyway, with what I've got so far, how can I implement the reset button so that when it is pressed, Q is set to 0 and Q' is set to 1 immediately, regardless of what state the clock is in?

Hello!

So I'm trying to solve an example which is probably going to come up on my exam next Tuesday. I'm not sure what I'm doing is right.

This is the circuit i'm given which includes a SR-latch. https://gyazo.com/e6b1079d8a92c42914f7a15efb45f6d4

a) Put up a transition table for the circuit and circle stable conditions.

b) Describe the circuits behaviour.

c) Is the circuit steady, explain?

Any tips on how to do this is greatly appreciated!

** EDIT ** Thanks for the help, everyone!

I am currently designing a basic circuit to simulate a traffic light. The circuit essentially functions as a finite state machine, moving from state to state (3 clock cycles for green, 1 for yellow, etc.).

I am trying to implement an asynchronous input to change the light for emergency vehicles, and usually for asynchronous inputs, I would utilize the Set/Reset inputs on the D flip flops in my design. However, in this case, I am looking to make the light immediately turn to yellow (regardless of current state), and then "begin" the yellow state at the next rising clock edge, moving to red and then looping on the red state until the vehicle passes.

The emergency vehicle is represented by a single input, and I am simply unsure of how to implement this design, or if it is at all possible using just D flip flops and basic logic gates.

Please let me know if I can clarify any part of my description.

Any ideas would be appreciated.

I am trying to do a hardware RNG based on ring oscillators on a Lattice MachXO2 board using the Diamond Lattice 2.2 suite. I am inexperienced (brand spankin' new, actually!) with FPGA technologies and have tried several approaches that did not do what I wanted so I am seeking some guidance. What I have tried so far is just doing simple things in VHDL.

signal ro0 : std_logic; ro0 <= not (not (not ro0))); -- this and several multi-line variations gave combinational loop errors or was shown to be optimized out in the post-synthesis place and route report, depending on whether I applied the keep or syn_keep attributes or left them off altogether

Googling around I found some Xilinx forums which recommended instantiating the loop with primitives. According to the MachXO2 documentation, the inverter primitive can be optimized out, so I tried to fake one with a LUT4 (its smallest primitive which does not carry the can-be-optimized-out warning) by ignoring pins A,B,C and letting the fourth pin be the inverter input and defining the lookup map as "1111_1111_0000_0000" (i.e. basically the inverse of pin D). I did get this to synthesize and was able to program the board but observed no oscillation, so I am wondering if the LUT is discrete in nature and may not feedback meaningfully?

I also tried to draw an inverter schematic with the schematic editor and this resulted in an infinite loop in synthesis with LSE and an error with Synplify (or vice-versa, I can't remember now!)

I am trying to "instrument" the RNG by piggy-backing on the oscillator-based LED blinker given here: http://www.eewiki.net/display/LOGIC/Lattice+Diamond+and+MachXO2+Breakout+Board+Tutorial What that is doing is hooking up the board's oscillator to an LED which blinks for your pleasure at a visually perceptible rate (i.e. on the order of hertz). So in the loop that toggles the LED, I have attached the output of the rng to another LED, and the inverse of the rng to a third LED; thinking that whenever the oscillator clock pulses I should see the RNG and not-RNG LEDs change too (likewise at a perceptible rate). I am definitely seeing the oscillator LED blink but the RNG and not-RNG LEDs don't ever change. Does this sound like a reasonable scheme for demonstrating/observing the RNG operation? Once I am confident that the RNG is working on the board I will probably try to find an oscilloscope and look harder at the RNGness of it all, but at this point I just want to finish figuring out how to do e

Now that I should hopefully be done with internship interviews for the rest of my life, here's a mega list of almost every interview question I was asked from 150+ interviews at Facebook, Apple, Amazon, Nvidia, Google, Microsoft, Qualcomm, Analog Devices, Texas Instruments, Northrop Grumman, SpaceX, Tesla, etc. This is going to be a massive step up from "part 1" that I posted a while back now that I have more coursework, internships, and interviews under my belt.

This was originally going to be part of the Interviews chapter of my internship search guide, but that post just got WAY too long so I decided to create a separate post just for this repository of questions. That post is still chock-full of interview advice and experiences, so check it out when it's ready! And before you get started, take a guess at how many questions this list has! (bonus points if you comment your guess because I'm also curious about your guesses!)

If you're reading this on Reddit (or not my website), check this post out on my website! You'll get this super cool table of contents bar that will make navigation much easier through this massive post. Any updates to this list will be reflected on my website, not this Reddit post or anything else. Also Reddit only allows posts up to 40,000 characters and my full list way exceeds that so you'll need to hop over to my website to get everything else. For some reason, Reddit has trouble recognizing my list so this Reddit post will have bullet points to identify questions, while my website has a BIG numbered list. And more importantly, you'll be giving me ad revenue!

Disclaimers and Notes

• These questions were for internships, but there's a lot of overlap with full-time (FT) interviews. In fact, I'm doing FT interviews at the time of writing this and they basically ask the same stuff, there are usually just more FT interviews so they have an opportunity to dive deeper and ask more questions I'd even say some of my internship interviews were harder/more in depth than my FT interviews. If the questions end up being super similar, I may just rename this post instead of making a new one lol.
• These questions are reflective of my s

Do your worst!

I'm surprised it hasn't decade.

For context I'm a Refuse Driver (Garbage man) & today I was on food waste. After I'd tipped I was checking the wagon for any defects when I spotted a lone pea balanced on the lifts.

I said "hey look, an escaPEA"

No one near me but it didn't half make me laugh for a good hour or so!

Edit: I can't believe how much this has blown up. Thank you everyone I've had a blast reading through the replies 😂

It really does, I swear!

They’re on standbi

Buenosdillas

The ’918 Patent 27. The ’918 Patent is entitled “Flash-DRAM Hybrid Memory Module.” Netlist owns the ’918 Patent by assignment from the listed inventors Chi-She Chen, Jeffrey C. Solomon , Scott H. Milton, and Jayesh Bhakta. The ’918 Patent was filed as Application No. 17/138,766 on December 30, 2020, issued as a patent on May 25, 2021, and claims priority to, among others, U.S. Application No. 13,559,476 filed on July 26, 2012, U.S. Application No. 12/240,916 filed on September 29, 2008, and U.S. Application No. 12/131,873 filed on June 2, 2008 as well as to two provisional applications, filed on June 1, 2007 (No. 60/941,586) and July 28, 2011 (No. 61/512,871). 28. Samsung had knowledge of the ’918 Patent no later than August 2, 2021 via its access to Netlist’s patent portfolio docket via notice of U.S. Patent Application No. 12/240,916 and U.S. Patent Application No. 12/131,873 on August 2, 2021.

• 10 -

Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 11 of 49 PageID #: 11 29. As summarized in the Abstract, the ’918 Patent discloses a memory module that includes a printed circuit board with an interface that couples it to a host system for provision of power, data, address and control signals, and additionally features “[f]irst, second, and third buck converters [that] receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.” Ex. 3, Abstract. 30. The ’918 Patent discloses, inter alia, a power module that provides power to various components of the memory system as depicted in Figure 16, shown below. 31. The ’918 Patent explains that “[t]he power module 1100 provides a plurality of voltages to the memory system 1010 comprising non-volatile and volatile memory subsystems

• 11 -

Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 12 of 49 PageID #: 12 1030, 1040. The plurality of voltages comprises at least a first voltage 1102 and a second voltage 1104. The power module 1100 comprises an input 1106 providing a third voltage 1108 to the power module 1100 and a voltage conversion element

Pilot on me!!

Dad jokes are supposed to be jokes you can tell a kid and they will understand it and find it funny.

This sub is mostly just NSFW puns now.

If it needs a NSFW tag it's not a dad joke. There should just be a NSFW puns subreddit for that.

Edit* I'm not replying any longer and turning off notifications but to all those that say "no one cares", there sure are a lot of you arguing about it. Maybe I'm wrong but you people don't need to be rude about it. If you really don't care, don't comment.

When I got home, they were still there.

What did 0 say to 8 ?

" Nice Belt "

So What did 3 say to 8 ?

" Hey, you two stop making out "

I won't be doing that today!

You take away their little brooms

This morning, my 4 year old daughter.

Daughter: I'm hungry

Me: nerves building, smile widening

Me: Hi hungry, I'm dad.

She had no idea what was going on but I finally did it.

Thank you all for listening.

There hasn't been a post all year!

[Removed]

Why

It’s pronounced “Noel.”

After all his first name is No-vac

What, then, is Chinese rap?

Edit:

Notable mentions from the comments:

• Spanish/Swedish/Swiss/Serbian hits

• French/Finnish art

• Country/Canadian rap

• Chinese/Country/Canadian rock

• Turkish/Tunisian/Taiwanese rap