Clock domain crossing Puns

Hi guys, Hope that you guys have a wonderful holiday!
I want to ask about the crossing clock domain in FPGA. I'm using a FIFO to store the data from the lower clock domain then take them out from another higher clock domain. For more specific, my input clock domain works at 2.5Mhz (of FIR FILTER) and the output clock domain works at 50Mhz ( clock of RMII interface )
I built a FIFO with a 2-bits length and 512-bits depth.
My question is should I separate the writing and reading or should I combine them? I mean should I wait until the data is full then start to take them out? It will significantly delay the data speed since the 50Mhz side needs to wait for the FIFO is full.
Thanks

FIFOs are out of the question unfortunately. 32 bit data bus on a 20 mhz clock has to be sent to a component running at 60 mhz. However, the data changes every clock cycle in the 20 mhz. What is the best approach to metastabalize the data bus? It also has a control signal that frames the data, but the control signal is also always asserted (until end of packet).

Is this doable? What is the best approach?

Hello,

I am beginning to learn VHDL and have a simple question. Basically I have an integer type that I want to cross over to another clock domain. I know that with a signal, you would have to use two or more flip flops to ensure signal stability. Is this also true for integers? My thinking was that during synthesis, the integer might be represented as a series of wires, and then when I use it in another process running at a different clock than the one it was set in, this might create metastability problems. If so, how do I deal with it, as I can't just pass an integer through flip flops.

Any information is appreciated

Thanks

Hi all.

I'm trying pass a signal from a slower clock to a faster clock, I thought it would be easy, all I had to do was double flop it on the receiving end (the faster clock) like pretty much every article says on the internet.

However, I have a rather unique clock generation setup which I think is causing me grief. My board supplies a 125MHz clock, I use a PLL to turn that in to a 100MHz clock, then I use a MMCME2 to turn that in to both a 371.25MHz and 74.25MHz clock for a 720p video signal. I can't go straight from 125MHz to the 720p clocks with a single primitive, I can get close but not exact, so I went with two clocking primitives.

I have logic that's supposed to generate the video data at a fast clock rate, right now that's being done on the 100MHz clock but I plan to move it to ANOTHER, faster clock, in the future after I figure these issues out. It's sending a pulse from the 74.25MHz to this faster clock which I'm stumbling on and I don't know why.

Here is the report: >Slack (VIOLATED) : -5.110ns (required time - arrival time)

> Source: processor_inst/begin_req_reg_replica/C

> (rising edge-triggered cell FDRE clocked by clk74_25 {rise@0.000ns fall@6.734ns period=13.468ns})

> Destination: processor_inst/begin_xreq_pipe_reg/D

> (rising edge-triggered cell FDRE clocked by clk100 {rise@0.000ns fall@5.000ns period=10.000ns})

> Path Group: clk100

> Path Type: Setup (Max at Slow Process Corner)

> Requirement: 0.034ns (clk100 rise@2330.000ns - clk74_25 rise@2329.966ns)

> Data Path Delay: 0.786ns (logic 0.456ns (58.015%) route 0.330ns (41.985%))

> Logic Levels: 0

> Clock Path Skew: -3.805ns (DCD - SCD + CPR)

> Destination Clock Delay (DCD): 5.864ns = ( 2335.864 - 2330.000 )

> Source Clock Delay (SCD): 10.040ns = ( 2340.007 - 2329.966 )

> Clock Pessimism Removal (CPR): 0.371ns

> Clock Uncertainty: 0.505ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE

> Total System Jitter (TSJ): 0.071ns

> Discrete Jitter (DJ): 0.329ns

> Phase Error (PE): 0.337ns

>

> Location Delay type Incr(ns) Path(ns) Netlist Resource(s)

> ------------------------------------------------------------------- -------------------

>

Hi!

I've got many registers in two domains.

I need to cross it. Access the registers in one domain from the other.

What is the most tried and true method to do this in the simplest manner?

Methods I've done for single bits:

Multiple samplings in the new domain and then false path the first jump from one domain to another in the sdc or multicycle the first jump.

However, if I have to do alot of crossing i.e. many registers, what would be recommended. I'd like to turn key this development since I do it so much.

My ideas are using dual port ram to do this. However I cringe at having to do addressed ram accesses for each register. Can someone recommend a simpler approach or Intel/Xilinx sanctioned approaches or IP blocks? Methods that work using both slow to fast and fast to slow?

Regards!

I have a signal, S, that I need to move from clock domain A to domain B.

• Clock A has a higher frequency than clock B (roughly 150 MHz vs 70 MHz).
• Signal S changes only every 2000 cycles (clock A) or so, so it can be considered "slow" or "stretched" (i.e. there is no problem sampling it in domain B).
• The value of the signal is non-critical to the design (it's mostly informative).
• The timing of the signal is not important (a few cycles delay in either domain is not an issue, neither is jitter or inacurracies).

As such, this should qualify as an easy clock domain crossing if I understand it correctly.

I have already implemented a double-flip-flop synchronizer, and the design works fine when running in my FPGA. However, the tool reports timing closure failures for the signal, and as a result reports a much lower FMAX for clock A than is really the case.

Essentially, I would like to tell the tool to ignore the timing of the signal (i.e. "I know what I'm doing"). What is the best way to do that?

I have a ECP5 dev board with open source toolchain, and my end goal is to build a sound card with ethernet input. Before buying a board with ethernet input, is there a simple project that I can do in my ECP5 dev board that uses multiple clocks?

I'm new to verilog, and I'm essentially teaching myself as I put together this proof of concept for a work project (sole designer, we usually operate in the mcu space but needed a cpld for regulatory reasons here). Short summary is the device is waiting for a dropped signal (nOutageDetect = 0) and will trigger a pair of relays to open and close after a 5s delay. when the signal returns (nOutageDetect = 1) the relays should switch after another 5s delay.

The TB waveform shows that this is happening exactly as designed, but when I try to reproduce it on my prototype test bed the delay stretches out to minutes.

source code:

`timescale 1ps/1ps

module prototype
(relayPos, nOutageDetect, capGood, openRelay, shutRelay, xferSwitch, plugType, manualOverride, LED_utilityPower, LED_dcMonitor, LED_0, LED_1, LED_2, gclk);

input wire relayPos;					// 0 = relay closed		1 = relay open
input wire nOutageDetect;				// 0 = signal lost  	1 = normal
input wire capGood;						// 0 = not charged 		1 = charged >14v
input wire plugType;					// 0 = add-on missing	1 = add-on connected
input wire gclk;
input wire manualOverride;

output reg LED_utilityPower = 1;
output reg LED_dcMonitor = 0;
output reg xferSwitch;					// switches secondary relay
output LED_0, LED_1, LED_2;				// LEDs programmed for demo debugging. utility likely to change
output reg openRelay = 0;               // trigger to open primary relay
output reg shutRelay = 0;               // trigger to shut primary relay

//pragma attribute LED_dcMonitor    	pinnum 4
//pragma attribute LED_utilityPower     pinnum 6
//pragma attribute LED_dcOverride   	pinnum 9
//pragma attribute manualOverride   	pinnum 40
//pragma attribute plugType 		    pinnum 5
//pragma attribute xferMonitor 		    pinnum 8
//pragma attribute nOutageDetect    	pinnum 20
//pragma attribute capGood		    	pinnum 34
//pragma attribute relayPos 		    pinnum 11
//pragma attribute shutRelay 		    pinnum 16
//pragma attribute openRelay 		    pinnum 14
//pragma attribute xferSwitch	    	pinnum 39
//pragma attribute gclk 		    	pinnum 43
//pragma attribute LED_0		    	pinnum 12
//pragma attribute LED_1		    	pinnum 17
//pragma attribute LED_2		    	pinnum 18

wire [2:0] LED;
assign {LED_2, LED_1, LED_0} = LED;

//////////////////////////////////////////////////
//
//	clocking block - 32kHz

Any book or tutorial with information on how to limit domain crossing schemes. I did not find a source where all the information would be in one place. Maybe someone knows such articles or a book.

I have not yet been able to find the source where they were considered from the simplest to the advanced cases.

I have a signal that I need to send between two asynchronous clock domains in an FPGA. Both clock domains have the same nominal frequency. The signal will be low most of the time. It will occasionally assert high for several consecutive clock cycles and then go low again for many many clock cycles.

The traditional way to handle CDC is to use two (or more) back to back synchronization registers. In Verilog for example:

reg x; // clocked in tx clock domain
reg y1, y2; // clocked in rx clock domain

always @(posedge tx_clk) begin
    x <= /* some logic from the tx_clk domain */;
end

always @(posedge rx_clk) begin
    y1 <= x;
    y2 <= y1;
end

My question is whether the following would get the signal across the clock domain safely and more quickly on average:

always @(negedge rx_clk) begin
    y1 <= x;
end
always @(posedge rx_clk) begin
    y2 <= y1;
end

Notice that the first sync register is now clocked on the falling edge of rx_clk. Since there is no logic between y1 and y2 it won't be difficult to meet timing even though there's only a half rx_clk period. Furthermore I would constrain the max delay from x to y1 to be less than the one half the nominal clock period.

So, is this safe (i.e. y2 won't see metastability in the next decade or two of continuous operation) and will it yield a clock domain crossing with lower latency than the traditional approach (on average). Or is this just foolishness?

There's a tool from Mentor called Questa CDC we've been using at my work for ASIC development. It does analysis on RTL and checks for any possible clock domain crossing issues that could result in metastability. It can be a bit cumbersome to use on large design as there can be a lot of noise to wade through to get at actual issues, and of course infrastructure to set up.

It seems like FPGA folks don't tend to run this kind of verification on their designs. A lot of times, the bulk of verification comes along with just slapping the design in FPGA and seeing how it works in real world as it's fastest. Cross clock domain issues in RTL can be extremely difficult to find though in real hardware (FPGA or ASIC).

Opinions? Thoughts? I'm wondering if anyone has seen the value to along with any kind of verification including directed test or constrained random, to run any CDC checking tools as well.

Let's say I have a shift register (called system A) that is operating at a clock frequency of 3f. The output of system A is fed into another shift register, system B, that operates at a frequency of f.

I want system B to read every 3rd output from system A. So do I even need to use any clock domain crossing systems such as an asynchronous FIFO or due to the unique nature of my problem (where I care about every 3rd output) can I just connect the two systems together?

P.S. If you are wondering why I care about every 3rd output, it has to do with a RAM based implementation of a shift register in Quartus.

Thanks!

Some times you need your one-clock-cycle-pulse-signal cross border of clock domains. If it cross this border from fast clock domain to more slow, it may cause of pulse loss. I want to describe here how to avoid that and related problems.

First problem you need to avoid is a losing of a short pulse. We can do it in this manner:

entity ClkXingModule is
    port (
        rst : in std_logic;
        OldClk : in std_logic;
        OldIn : in std_logic;
    
        NewClk : in std_logic;
        NewOut : out std_logic
    );
end entity ClkXingModule;

…

Xclk : process (NewClk, OldIn) is
    begin
        if OldIn = '1' then
            NewOut <= '1';
        elsif rising_edge(NewClk) then
            NewOut <= '0';
        end if;
    end process Xclk;

But in this case we can have a trouble if OldIn ramps up and down just before rising_edge(NewClk). In this case NewOut will be reseted shortly after it will be set and we will have a NewOut pulse with length equal to length of OldClk (not a NewClk). It may cause a problems due to the fact that all our circuits in NewClk domain designed for a long signals, longer than a OldIn pulse. So, we modify our code.

Xclk : process (NewClk, OldIn) is
    begin
        if OldIn = '1' then
            Unstable <= '1';
            NewOut <= '1';
        elsif rising_edge(NewClk) then
            NewOut <= Unstable;
            Unstable <= '0';
        end if;
    end process Xclk;

But we still have a issues with a metastability and racing on signal NewOut when it became high simultaneously with NewClk event. Let’s fix them.

Xclk : process (NewClk, OldIn) is
    begin
        if OldIn = '1' then
            Unstable <= '1';
            Stable_meta <= '1';
        elsif rising_edge(NewClk) then
            Stable_meta <= Unstable;
            Unstable <= '0';
        end if;
    end process Xclk;
   
process (NewClk, rst) is
        begin
            if rst = '1' then
                NewOut <= '0';
            elsif rising_edge(NewClk) then
              NewOut <= Stable_meta;
            end if;
        end process;

If we add an option to make our output signal one clock cycle sh

So, I'm reading in 8 bits of data from a 27MHz chip into a 100MHz FPGA. I'm using a simple CDC flip flop cascade to make sure I receive valid data from the 27MHz chip. It looks like this: http://i.imgur.com/dmCFuTf.png

What I'm trying to figure out is how to detect when the value coming out of DFF 3 is new data, not necessarily a new value. I need to know exactly when the data going into DFF1 comes out of DFF3. Would using some counters to count clock cycles be a reliable way. As in, after you count one cycle from clock1 then count 2 cycles from clock2, you can assume the data going into DFF1 is now coming out of DFF3?

Hopefully someone can give me some advice. It seems like a trivial task, but counting the clock cycles doesn't seem like the proper way of doing this.

Thanks!

I am trying to apply CDC from a faster to a slower clock domain but I couldn't do that. I am using xpm_cdc_handshake macro. But it allows only CDC from a slower to a faster clock domain. It is said "...verify that dest_clk can sample src_in[n:0] two or more times." at page 16 of UG974. What can I do?

Can anyone suggest me a good source for multi clock domain based RTL development. Also to prepare for CDC based design interviews. I'm fetching for a source explaining a different scenarios of metastability and using CDC techniques.

Hey all,

I am not allowed to use FIFO's for this design. Luckily, the 60mhz data has a frame that pulses every 3 clock cycles along with changing the data. So essentially, the data nus on the 60mhz clock changes at a rate of 20 mhz. However, I still need to sample the data on the actual 20 mhz clock whenever frame is high.

If I have two state machine in two different modules running off two separate clocks, what is the safest way of triggering one from the other? Ideally I would like one flag that is set by the trigger state machine and reset by the triggered state machine once he operation has finished however this obviously isn’t possible due to the two clock domains. In this case is he best method a start -> and a done <- flag? How do you build a water tight protocol?

Assuming I have 2 phase locked clocks coming from the same PLL, say a fast 50MHz clock and slow 1MHz clock.

If I update a signal based on the fast clock, and want to latch it for a on the slow clock, will the timing tools take the clock differences into account? Do I need to worry about setup time violations if I update the signal 1 fast clock tick before common fast/slow tick?

Basically, I have a Done signal, which will only be high for 1 fast clock. When this signal goes high, I want to send a 1 cycle slow clock based pulse.

Am I overthinking this? Thanks!

https://www.reddit.com/r/fitbit/comments/i5hog8/adblocking_which_urls_do_fitbit_store_and/

About a year ago I posted this to share what I've found regarding adblockers interfering with the "clock faces" and "apps" function of the fitbit app.

Since about 2 months ago the problem have once again surfaced, but this time I haven't had time nor the need to urgently figure out which URLs fitbit doesn't like this time around. Well I finally decided to identify the domain names, and here they are:

*.google-analytics.com     
cdn.optimizely.com

So for those who are using adblockers and are having troubling accessing these fitbit features, if you want you can add the above two to your adblocker whitelist.

Hope this helps.

So it’s been quite a week (see post history if you care) and this happened this morning and I’m currently waiting to give my statement to school resource officer so here goes. I’m getting my masters in education, I student teach but I also work part time as a para pro for our school district.

One of my jobs is to set up the student cross walk in the morning. The signs for the crosswalk are stored on the side of the street literally steps away from where I park. So every morning I would arrive a little early, go put out the cross walk on time and then go clock in.

We had a district time keeping audit and it came out that I had to clock exactly on time and can’t put out the cross walk signs until I’m clocked in. This means the cross walk physically can’t be set up until 10 minutes late because it takes 10 minutes qto get my laptop, clock in and back to the crosswalk. District adjudicator was such an asshole said that’s the way it had to be and kids can adjust or just wait the 10 minute to cross the street. I’ve been doing it “right” every day since.

Well the kids didn’t wait and this past week it’s basically been that old video game frogger with kids in the street. This morning, One kid literally stepped in front of a car who had to screech on his brakes, which caused him to get rear ended and that car in turn got rear ended. 6th graders are not the best decision makers so instead of going back to the curb; the kid ran across the other lane and caused another accident in that lane. Street is not super busy but it still had to be shut down since so many cars were involved. Since a lot of the cars are parents of our students, a huge number were late. The kid who was almost hit was taken home and I wouldn’t be a bit surprised if his parents (problems in thier own right) seek money from the district through an over blown lawsuit.

By all means, enforce those clocking in rules. The district “saved” its self maybe $5 by not letting me clock in early.