Any progress since the hopfield network? Content addressable memory seems very important concept , couldn't find anything similar in deep learning. Anything?

I'm looking for studying resources on memory models for storage and recall of sequences, particularly associative and auto-associative recall of such sequences. Ideally I would like a textbook on this with exercises at the ends of the chapters and actual sourcecode. I actually want to learn the topic towards the aim of implementation.

(These might be Boltzmann Machines, Hopfield Networks, or SOMs, but it is unclear whether these were ever used for sequences.)

Russell and Norvig's AIMA does not cover this topic in any level of detail that I need, being a historical survey text. I am primarily focused in models that are not trained by backprop, but instead rely upon local changes to synaptic weights in a unsupervised manner. Although I don't mind reading some chapters on supervised learning methods too. Thanks.

To give a better idea of the material I am wanting to dig into , I give the two following abstracts, both of which are from the 1980s. (Yes, the 1980s). I'm hoping there is some updated textbooks and materials on this topic.

Associative Memory in a Simple Model of Oscillating Cortex (1990)

> The network has explicit excitatory neurons with local inhibitory interneuron feedback that forms a set of nonlinear oscillators coupled only by long range excitatofy connections. Using a local Hebb-like learning rule for primary and higher order synapses at the ends of the long range connections, the system learns to store the kinds of oscillation amplitude patterns observed in olfactory and visual cortex. This rule is derived from a more general "projection algorithm" for recurrent analog networks, that analytically guarantees content addressable memory storage of continuous periodic sequences - capacity: N /2 Fourier components for an N node network - no "spurious" attractors.

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Adaptive bidirectional associative memories (1987)

> Two fields of neurons, FA and FB, are connected by an n X p synaptic marix M. Passing information through M gives one direction, passing information through its transpose M^T gives the other. Every matrix is bidirectionally stable for bivalent and for continuous neurons. Paired data (Ai,Bi) are encoded in M by summing bipolar correlation matrices. The bidirectional associative memory (BAM) behaves as a two-layer hierarchy of symmetrically connected neurons. When the neurons in FA and FB are activated, the network quickly evolves to a stable state of twopattern reverberation, or pseud

I have been reading around a bit about computational models and memory organizations used in modern computers, and I don't understand CAM. I know that it is good for high-speed searching algorithms, but I don't understand why. If you need to look through the whole memory segment and check if every word matches the one you're looking for, isn't that super slow?

HYPOTHESIS AND THEORY article

Front. Mol. Neurosci., 25 February 2021 | https://doi.org/10.3389/fnmol.2021.592951

The Mechanical Basis of Memory – the MeshCODE Theory

📷Benjamin T. Goult*

• School of Biosciences, University of Kent, Canterbury, United Kingdom

One of the major unsolved mysteries of biological science concerns the question of where and in what form information is stored in the brain. I propose that memory is stored in the brain in a mechanically encoded binary format written into the conformations of proteins found in the cell-extracellular matrix (ECM) adhesions that organise each and every synapse. The MeshCODE framework outlined here represents a unifying theory of data storage in animals, providing read-write storage of both dynamic and persistent information in a binary format. Mechanosensitive proteins that contain force-dependent switches can store information persistently, which can be written or updated using small changes in mechanical force. These mechanosensitive proteins, such as talin, scaffold each synapse, creating a meshwork of switches that together form a code, the so-called MeshCODE. Large signalling complexes assemble on these scaffolds as a function of the switch patterns and these complexes would both stabilise the patterns and coordinate synaptic regulators to dynamically tune synaptic activity. Synaptic transmission and action potential spike trains would operate the cytoskeletal machinery to write and update the synaptic MeshCODEs, thereby propagating this coding throughout the organism. Based on established biophysical principles, such a mechanical basis for memory would provide a physical location for data storage in the brain, with the binary patterns, encoded in the information-storing mechanosensitive molecules in the synaptic scaffolds, and the complexes that form on them, representing the physical location of engrams. Furthermore, the conversion and storage of sensory and temporal inputs into a binary format would constitute an addressable read-write memory system, supporting the view of the mind as an organic supercomputer.

1. I do not understand why only one byte can be addressed by a single memory address? Are only RAMs word-addressable, or do other technologies use this trick as well?
2. I understand that the communication protocol of the system bus implies the size of the address space, but does the CPU's bittness also affect the size of the address space? If yes, how?

Is there any efficiency reasons behind the computability of an 8 bits byte versus, for example, 4 bits? Or is it for structural reasons behind the hardware? Is there any argument to be made for, or against, the 8 bit byte?

I have to change a bunch of lb vservers on Citrix ADC to non addressable (IP:0.0.0.0 Port:0) and put them behind content switches. There are many so I'd like to do it from CLI, or ADM config job. However it doesn't seem to work and I swear I figured this out a year or two ago. Does anyone know the command to change the IP and Port of a regular LB vserver to non addressable from CLI? The command to add one is "add lb vserver tst_nonaddr SSL 0.0.0.0 0 -persistenceType NONE -cltTimeout 180" but no version of the "set" command to change to this seems to work.

Let's say you have a CPU that can access 2GB of RAM maximum.
That shouldn't stop the computer from using a cache on a Flash drive that exceeds that capacity to superfetch files that are commonly used from the CPU, to avoid having to read them from the slower HDD if it can't store them in the limited RAM.
My intuition tells me that, that should be the case because Readyboost is a different way to add memory to a computer, than inserting a RAM stick with which the PC has to work and functions much like the swap file on the HDD does.

I am aware of the drawbacks of doing this, by the way, this is just curiosity on my part.

32 bytes of of addressable sequential access memory.

This one doesn't have the circuitry to be addressable, but it is possible.

16 bytes per "disk".

The hole thing can be stacked upwards easily because its 2 blocks tall.

I'm pretty awful at redstone so its not the smallest thing, can be probably compacted alot.

Edit: with addressable i mean for example: 128 bits in one "disk" can be addressed to 16 one byte addresses.

U could address the 16 byte disks themselves too.

https://i.redd.it/ovz6b8e9gks11.png

For me, I think I'd say many of Javonte's runs are up there, especially the one against the Ravens where he carried Marlon Humphrey like 20 yards and got the Angry Runs award for that week.

But my unquestionable favorite memory is going to the Chargers game a few weeks ago and getting to see PS2's pick-six in person. The whole stadium just erupted. Everyone was on their feet yelling and screaming and it was amazing

I build a simple, addressable and tileable memory-cell array with a built-in binary display. It uses 12 combinators (8 deciders, 3 arithmetic, 1 constant), stores one 16-bit value per cell and a cell is 6x7 tiles in size. With addressable, I mean that you can write to/read from any cell in the array over only 2 wires (1 red, 1 green). Blueprint (3 Cells)

https://preview.redd.it/wz7vg05ng1821.png?width=473&format=png&auto=webp&s=11da610027e8ebea212dcf2d4cb4b4ed44aabfbd

https://preview.redd.it/uws3e656f1821.png?width=474&format=png&auto=webp&s=2c953975e0cf23de432dbfc4f4349c597ca54e85

Legend:

• Dark Blue: Binary display of the stored value
• Medium Blue: Lamps signaling read/writes
• Light Blue: Lamp controls
• Red: Address handling
• Yellow: Diodes
• White: Limiter to ensure only 16-bit values are stored
• Pink: Write handler
• Green: Read handler
• Black: Storage

The usage is quite straight-forward. The red wire is used as input and the green wire is for the output. There are 4 signals (R, W, A, S) and you can store and read values.

• Read a value: If R (red wire) is non-zero, the value of the cell with the address in signal A (red wire) will be sent using the signal S (green wire).
• Write a value: If W (red wire) is non-zero, the value of the cell with the address in signal A (red wire) will be set to whatever (only the 16 lower bits) S (red wire) is.

A few notes on timings, speed, and parallel reading and writing:

• The output of a read is delayed by 3 ticks, so 3 ticks after R and A are sent on the green wire will deliver the output for as long as R and S were sent. It takes the value 1 tick to get from the actual storage to the green output wire.
• A write needs the input for at least a single tick, so pulsing W, A, and S will write properly, but it will take 3 ticks before the value reaches the actual storage. Holding the values for longer will work as well.
• Reading and writing the same cell at once is possible, but you will receive the old value in the cell for exactly 1 tick. After that, you will receive the newly written value. This means, that pulsing R, W, A, and S will cause the green wire to pulse the old value of the cell for 1 tick, after 3 ticks. Reads after that after that will return the new value.
• Inputting commands each tick is possible, meaning you can, for example, read for the first tick and write again in the tick right after.

It is a joke that NVAX would trade down on the SCOTUS news - that means nothing. The W.H.O. had a goal of vaccinating 40% percent of the population in every country by YE 2021 and they did not hit the goal. The new goal is 70% of population in every country by mid 2022. The lowest rates of vaccination are in the developing world where NVAX will have much greater uptake because it can use traditional cold chain storage. In the developing world we are looking at a annual shot or booster. The groups still to be vaccinated are kids (data suggests kids have less reactions to NVAX) and some anti-vax types may convert with a non-mRna - traditional protein based vaccine. The addressable market is every person on earth. COVID is here to stay and it will be an arms race between vaccine manufacturers and the Virus Variants. NVAX will start leading that battle and we should get behind them. (Disclaimer - Despite getting crushed yesterday. I am all in on NVAX $240K in stock and Feb, Mar and April call options today worth $210k total today). The only real risk is if they run into manufacturing or quality issues. They have had some time to address these so I think it is safe to believe the will really ramp up and deliver. The stock is at a 52 week low and the news flow will be very strong for the next 90 days. Consensus price tragets call for a double..... don't see opportunities like this often.

https://preview.redd.it/u4mp22e3uvb81.png?width=2524&format=png&auto=webp&s=0198684fd1bca7b29f39a46bc3c1d40d8e9b2789