SystemVerilog Puns

Someone recommended verificationacademy.com to me previously, and it's unbearably awful. It's just a series of videos. In each of them, the narrator puts up a selection of source code on the screen, then narrates over it line by line. Then the next slide where it's pretty much the same thing. No real structure or syllabus there.

Are there any good resources for learning verification?

I’m trying to create a union with a shortreal field and a 32 bit reg or int field so I can view the hex or binary representation of the shortreal on the simulation waveform. But the int field representation of the float value is wrong. Here is my syntax:

typedef union{

shortreal float;

int int_field;

} test_input;

test_input input_vector;

initial begin

input_vector.float = 1.25;

/**/ #10 input_vector.float = -1.23986;

end

But the int_field has values 0 and 32’h4b2b777d for 1.25 and -1.23986 respectively. The actual hex equivalents of 1.25 and -1.23986 are 32’h3fa00000 and 32’hbf9eb3a2 respectively. I’m using modelsim, but I get the same results in Vivado’s builtin simulator (does it have a name? Like ‘Vivadator’ or something?) Can anyone explain what I’m doing wrong?

A friend and I built a website for practicing SystemVerilog interview questions (similar to Leetcode). Our core coding and simulation features are done, and we’re working to add new questions and make the site look more professional.

Link: chipdev.io

Are there any questions you’d like to see added? Or other areas we can improve in? We’d love to get some feedback on how we can improve the site and make it better for everyone.

https://preview.redd.it/oc550ken3ct71.png?width=1910&format=png&auto=webp&s=9d2da8169ff7af715547d902d0e3ad3f86e3b010

Using basic SystemVerilog, or by UVM.

Like for learning Verilog, I've been using hdlbits (https://hdlbits.01xz.net/wiki/Main_Page). But that's for Digital Design using Verilog. Are there any similarly good websites to learn how to do Design Verification using SystemVerilog ?

So, for the last couple days I have been working on creating a BCD incrementor on my Nexys A7-100T. I started by creating the binary to BCD converting module. I tested it quite thoroughly, and I say with 99.99% confidence that it functions as intended.

Where I'm having trouble now is the actual 7 segment display module. For some reason, I am not getting an output for my anode, and my output for the cathodes is not what it should be. I have been sitting here for a while trying to understand why that is, but I can't seem to figure it out. Perhaps I am thinking too much like programming and not enough like hardware, but I am definitely stuck. When trying to troubleshoot an issue with your design, how do you go about doing it? Are there any steps that I should try to take?

Also, in Vivado, is there a way that I can get some of my internal module signals to display on the simulation graphs? Thanks.

I'm looking for suggestions on what to do next? What I've covered so far is some projects and systems with FSM and decent test benches.

I think reading an advanced book about design would help me a lot; in which the author would probably discuss certain design issues and scalability etc and its Verilog code. Most of the books I've found cover the same basics and I think I'm no longer a beginner. Do you have any suggestions on that?

or Should I learn SystemVerilog as a progression to Verilog?

Also, I've read this q&a on SE about design patterns or "models of good practices" in HW design, but it's 10 years old, what should I look into? https://electronics.stackexchange.com/questions/14133/is-there-a-design-patterns-for-synthesizable-rtl

Or should I learn & do advanced projects to get to an intermediate or advanced level? please suggest some, the type that forces me to think about better design.

This question might be repeated as I feel it's somewhat generic; please, feel free to throw in some links, that'd be much appreciated. I'll read them.

Thank you

How to add systemverilog features to Vivado Xcelium simulation environment?

The Simulator Language selection are: Verilog/VHDL/Mixed

How to add System Verilog??

https://preview.redd.it/8dah7p6q8yy71.png?width=884&format=png&auto=webp&s=8ab1f6142e30fa6f18bad5679f605bc7099d5c2d

I am tinkering with classes in SystemVerilog and ran across an issue in Vivado (works with ModelSim).

my_package.sv:

package my_package;
    class my_class #(
        parameter FOO = 3
    );

        typedef logic [FOO-1:0] foo_t;

    endclass : my_class
endpackage : my_package

my_module.sv:

module my_module (
    some_input,
    some_output
);
    localparam integer BAR = 15;

    import my_package::my_class;

    input my_class#(.FOO(BAR))::foo_t some_input;
    output my_class#(.FOO(BAR))::foo_t some_output;

    always_comb begin
        some_output = some_input * 2;
    end
endmodule : my_module

Creating a Vivado (2019.2 and 2021.1) project with just the two files above and the my_module.sv set as the top results in the following error: ERROR: [Synth 8-660] unable to resolve 'FOO' [/home/foobar/vivado_error/my_package.sv:6]

But, if I change my_package.sv to have typedef logic [my_class::FOO-1:0] foo_t;

Instead of typedef logic [FOO-1:0] foo_t;

Then there are no errors, but the value of BAR does not get passed to my_class and my input and output ports end up with 3 bits instead of 15.

The whole reason for messing with this is to find a nice way of being able to avoid having to define the same types all over the place (test benches, synthesized code, ports, etc). I fully understand that not all of SystemVerilog works in Vivado, and not all of it is even synthesizable. Would be nice if it worked though :)

Running with ModelSim shows the correct bit widths on the ports. But that's not terribly surprising.

Anyone have a clue as to why this doesn't work? Am I trying to do something that's not supported in synthesis? Is this just a limitation of the vendor tools? I might try this out on Synplify if I have time.

Thanks!

-Proto

Hi all,

I'm still working my way through 'FPGA Prototyping by SystemVerilog Examples' by Pong P. Chu.

I made it to chapter 7, about FPGA embedded memory and FIFOs. It looks to me like there's a logic error in the FIFO Controller Design presented in listing 7.7. (included below).

The controller allows for simultaneous reads and writes with the following case statement:

2'b11: // write and read
    begin
       w_ptr_next = w_ptr_succ;
       r_ptr_next = r_ptr_succ;
    end

The full and empty signals are left untouched because read and write pointer advance at the same rate.

~full is assigned to the register file's write enable, so writes can only occur if the fifo is not full:

	// write enabled only when FIFO is not full
   	assign wr_en = wr & ~full_tmp;

That all sounds reasonable enough. However, the problem is that if the FIFO is full and you then get one or more simultaneous reads and writes, the read and write pointer will advance, but the write data never enters the fifo. The waveform below shows the problem.

https://preview.redd.it/qww44n3pdzd71.png?width=990&format=png&auto=webp&s=a72e0a620f93d4c1af33962c97a5baf85c4401f9

The FIFO is 16 bytes deep. After reading the initial 16 bytes of data, the FIFO starts to emit stale data. rd_data stays at 8'haa. The 8'hbb wr_data value never enters the FIFO. Or am I making a rookie mistake again?

In software I avoid the whole FIFO full/empty complication by not allowing a FIFO to go completely full, i.e. wr_ptr==rd_ptr means empty and wr_ptr+1==rd_ptr means full. Wouldn't that be a reasonable solution here as well?

The code:

// Listing 7.7
module fifo_ctrl
   #(
    parameter ADDR_WIDTH=4  // number of address bits
   )
   (
    input  logic clk, reset,
    input  logic rd, wr,
    output logic empty, full,
    output logic [ADDR_WIDTH-1:0] w_addr,
    output logic [ADDR_WIDTH-1:0] r_addr
   );

   //signal declaration
   logic [ADDR_WIDTH-1:0] w_ptr_logic, w_ptr_next, w_ptr_succ;
   logic [ADDR_WIDTH-1:0] r_ptr_logic, r_ptr_next, r_ptr_succ;
   logic full_logic, empty_logic, full_next, empty_next;

   // body
   // fifo control logic
   // logicisters for status and read and write pointers
   always_ff @(posedge clk, posedge reset)
      if (reset)
         begin
            w_ptr_logic <= 0;
            r_ptr_logic <= 0;

Can someone recommend any learning resources for Real Number Modeling in SystemVerilog for Mixed Signal verification?

I've got all sorts of problems with my .sv files in Vivado. Sometimes after re-synthesis all of a sudden there are undefined parameters, interfaces missing, all sorts of jazz. Can somebody describe a reliable strategy (for both IP creating and overall design)?
For example, I use packages. One package - one file. Should it be .svh or .sv?
In my case I found it should be .sv file with `ifndef guard and I should `include + import::* it in all files which seems clunky and prone to some errors (because in `include you descrive the relative path and it could lead to failure if the file in /sim and you need to use it in /synth etc)

Another one with classes. One kinda helpful advice was to make a package consisting with `include directives for all of my files with class definitions.

So what I want to know is:

1. When to use .sv and .svh files.
2. How to manage folders to reference all files without pain and keep them all under git.
3. Which SystemVerilog features are reliable to use: packages, programms etc.
4. Is `include a bad practice and how to write a reliable filepath to easy migrate.
5. Are blockdesigns bad and should I just use plain text files with TCL workflow?
6. Any other pro-tips about files and systemverilog features in Vivado.

I built a filter and implemented it in HDL. I'm new to DSP and sort of new to FPGA design. I was wondering if some of you would be willing to take a quick glance at my matlab code, verilog implementation, and system verilog testbench and give me some professional feedback. Sort of like r/roastme, but roast my code instead. I put the github link at the bottom of the post.

I'm open to all advice and criticism. I'm trying to do projects to add to my resume to make myself standout from the competition. Project-wise, where would you suggest I go from here to impress recruiters/interviewers?

Abstract:

I created a noisy signal and a low pass filter in matlab. I then implemented the filter as a fixed point difference equation in matlab, compared it to the original floating point implementation, exported the input signal, output signal, and filter coefficients as hex values stored in text files, and finally implemented the filter as a fixed point difference equation in HDL.

github code

Hello,

I'm entering 2nd year of ECE and I really like Designing Electronics Either Analog or Digital, and I was wondering on taking an external course for a better understanding and becoming more innovative and so.

So I thought that the best idea was to take a HDL course that will help me in the future. Is it a good idea to take it or should i take something else or should i wait for my Micro Processor Course in uni first? P.S: I've Already taken basics of Digital Design.

If it is a good idea can u link me to the best online Verilog course out there please?

Hi all,

I'm working my way through 'FPGA Prototyping by SystemVerilog examples' book from P. P. Chu.

I'm a bit confused about the Mealy machine based edge detector in section 5.3.1. I'll copy the source code below.

It looks like if a rising edge occurs immediately before the rising edge of the clock, the resulting 'tick' pulse can be super short. So short in fact, that it doesn't even show up in simulation (see first two pulses in attached waveform). Isn't this a recipe for missing rising edges?

This book comes highly recommended as a resource for learning FPGA programming, so it's probably me making a mistake here, not the book, but I don't see it.

Thanks for any insight.

Ruben.

module edge\_detect\_mealy  
   (  
    input  logic clk, reset,  
    input  logic level,  
    output logic tick  
   ); 

   // fsm state type  
   typedef enum {zero, one} state\_type; 

   // signal declaration  
   state\_type state\_reg, state\_next; 

   // state register  
    always\_ff @(posedge clk, posedge reset)  
       if (reset)  
          state\_reg <= zero;  
       else  
          state\_reg <= state\_next; 

   // next-state logic and output logic  
   always\_comb  
   begin  
      state\_next = state\_reg;  // default state: the same  
      tick = 1'b0;             // default output: 0  
      case (state\_reg)  
         zero:  
            if (level)  
               begin  
                  tick = 1'b1;  
                  state\_next = one;  
               end  
         one:  
            if (\~level)  
               state\_next = zero;  
         default: state\_next = zero;  
      endcase  
   end  
endmodule 

https://preview.redd.it/un1sfyogusa71.png?width=1177&format=png&auto=webp&s=79ebd78e0fa39db2a2ce9eca3be2b74375ff8ae2

I've been wanting to get more familiar with SystemVerilog for a while now, but I can't seem to find a way to get Vivado to explicitly understand SystemVerilog. Like, I haven't actually tried to use SystemVerilog, I always just look for a setting where I select SystemVerilog instead of Verilog.

Now I'm even more curious since the company I'm interviewing for seems to use SystemVerilog. I was able to catch that "logic" is a keyword in SystemVerilog, and that "always_ff" is also used in SystemVerilog, but next week I have my second interview, this time with RTL coding instead of RTL design, and it sounds like there will be some SystemVerilog

EDIT: thanks for the replies. It looks like under source file properties I can change from verilog to like 20 different languages I didn't know existed (including SystemVerilog)

Thanks for the help

Hello,

I am looking to learn more about hardware verification using SystemVerilog. I just finished my Bachelors and I am trying to expand my experience with FPGAs as well to help me in my search in FPGA jobs. What are some of your recommendation of sources to learn SystemVerilog from? What are some project ideas you may have as well for someone who is learning SystemVerilog (guessing projects using PCIe, ethernet, JTAG ,etc.)). Also, what are your recommendations for FPGA development boards to use in these type of projects?

Quick edit: I forgot to mention which of the testing methodologies (OVM or UVM) should I be more focused in learning as well?

Thank You.

Hi, I've wrote a code in systemverilog which counts how many bits are equal to '1 in a bus. (not school or work related, just playing with EDA). It works.

But can this be synthesis? and would apricate any input if you see anything that can be done/written better or even enlighten me, methodically wise .

EDA playground direct link: https://edaplayground.com/x/9fR8

*I'm capturing the bus when data is valid. Then I go over each bit until no more ones in the captured value. Once no more ones, I assert 'ready',

In parallel to the link above, I'm attaching the code here as well. Thank you

module one_bit_counter# (N=4)(

input logic [N-1:0] a,

input clk,rst,valid,

output logic [N:0] ones,

output logic ready);

logic [N-1:0] a_rotated;

always_ff @(posedge clk) begin: capture_input_rot

if (valid)

a_rotated <= a;

else

a_rotated = a_rotated >> 1; //rotated right by one, insert zero from the MSB

end: capture_input_rot

always_ff @(posedge clk) begin: bit_iterate

if (rst)

begin

ones <= '0;

end

else if (a_rotated[0])

begin

ones <= ones + 1;

end// else if

end: bit_iterate

assign ready = ~|a_rotated; //if no more ones in a_rotated, ready is asserted

endmodule

Hello guys, From my internship, I do a lot of RTL design and synthesis. I realized that there are so many things that I do not know and I was wondering if you guys could suggest any sources, platforms where I could learn and practice Verilog/SystemVerilog from beginner level to advance. Thank you in advance.

I'm working on my masters thesis writeup and have a reasonably complex verification framework (not UVM but based on UVM ideas). This consists of a bunch of classes with parameterised types, and classes that extend those. I'd like to generate UML diagrams to describe this in the simplest way possible. I haven't drawn any UML diagrams since my undergrad more than a decade ago, so I'd prefer not to use something like draw.io to create them manually, as I'd probably make mistakes or would have to spend ages getting back up to speed.

Ideally there would be a tool that parses the SV and creates the diagrams for me, which I could then edit to tidy them up. In second place would be a simple tool that lets me input the info manually: (Y is abstract, contains these methods, X extends Y and overrides these methods, ...).

Any suggestions?

Coding in (sys)verilog is hard in a large project. You have a large number of modules, deep hierarchies and infinite number of nets.
Do you know any plugin for visual studio code, eclipse or a complete editor what capable for the followings:

• show a net driver(s) and connected modules through hierarchy
• generate module instantiation
• check functional "syntax" error
• connect sysverilog interface to verilog "interface" code generator

What do you recommend? I am ready to write my own if I have to but only if I have to. I could use iverilog for functional check but still I would need a parser to write everything by myself.

I come from having developed for few years in VHDL primarily and recently started using SystemVerilog for some modules at my work.

I am actually amazed by how forgiving SV is really. The automatic extension is fine, however automatic truncation is what bothers me.

For example,

wire [18:0] a;

wire [16:0] b;

assign b = a;

is completely fine in SV while VHDL would be screaming that I just assigned two width mismatched signals, and just lost 2 bits (in monospace text 6 and 8 are very similar looking)

Is there any way to enable more pedantic language checks for SV in Vivado/Quartus ?

Hi, I am looking for Logic Design and Verification Using SystemVerilog by Don Thomas!

Thank you!!

Another best practices question.

I am trying to get rid of millions of warnings in Vivado coming from my usage of SV interfaces.

So I've got a master module with a master modport with a bunch of signals. And there are a lot of slaves with different modports. Looks something like snippet below. In a real design I use this approach for the AXI control/status registers, for example.

interface demo(input logic clk);

	logic [31 : 0] signal_0;
	logic [31 : 0] signal_1;
	logic [31 : 0] signal_2;
	logic [31 : 0] signal_3;
	logic [31 : 0] signal_4;
	logic [31 : 0] signal_5;
	logic [31 : 0] signal_6;

	modport master
		(
			input clk,
			output signal_0,
			output signal_1,
			output signal_2,
			output signal_3,

			input signal_4,
			input signal_5,
			input signal_6
		);

	modport slave_0
		(
			input clk,
			input signal_0,
			input signal_1,
			output signal_4
		);

	modport slave_1
		(
			input clk,
			input signal_0,
			input signal_3,
			output signal_5,
			output signal_6
		);

Some of them share the input signals from the master, some of them don't use all of the signals of the interface, that's why I am getting a lot of warnings about "undriven/unconnected nets".

So my question is how to deal with that?

Create a bunch of interfaces with master\slave pairs that uses all of their signals?

Put every signal in every modport and somehow shorten them at the slave's end?

Or something else?

Hi all,

For any of those chip designers / verification engineers coding in Verilog or SystemVerilog, please check out my script. It’s the fastest and most accurate available (IMO).

https://github.com/nachumk/systemverilog.vim

The easiest way to install the script is to follow the README on the GitHub page.

In addition to syntax highlighting and indenting, you can also enable these additional features (if enabled via .vimrc):

matchit - Using shift-5 (%) to hop between starting and ending tokens begin → end → begin module → endmodule → module ( → ) → ( function → endfunction → function and many other examples folding - Using zc and zo to hide portions of text based on indented sections Replacing tabs with spaces by re-indenting the complete file To use systemverilog.vim you can visit the GitHub page:

This script is not OVM/UVM aware.

Feel free to share feedback. Thanks!

Hello, I am using Vivado 2019.2 coding in SystemVerilog and am trying to use an array with 15 rows and 8 columns with 5 bits at each location.

I initialized the array as: logic [4:0] data [0:14][0:7];

When I ran synthesis Vivado gave the warning that "3D RAM for this pattern/configuration is not supported. This will most likely be implemented in registers." Is there another way of declaring this array that will avoid this issue? Each location does not necessarily need 5 bits of data, just 5 bits or more.

I am currently writing code to drive an LCD. I am driving a task from an outer always loop. A static task keeps an internal counter and is responsible for actually timing and sending the command to the LCD. Basically, I intended the case(counter) keeps track of which command should be sent, while case(pulse_counter) keeps track of what part of the command is being sent (in this case, lcd_e signal is pulsed high for 12 clocks, with a specific signal on lcd_dbh, then there is a significant delay before the next pulse. The outer counter should only increment when the command has been fully completed. At least that is the intended behaviour.

However, it seems that the outputs are not quite updating correctly. If at the end of a command sequence I set pulse_counter to 0, I would expect lcd_e to go high the next clock cycle, and for the lcd_dbh signal to change if required. The only way I was able to make this work in simulation was if I set pulse_counter = -1 and the end of a command sequence , and then there is still an additional clock delay (from what I would have expected) until the lcd_e signal goes high (I would expect to to go high after the clock cycle where pulse_counter = 0, but instead it goes high after pulse_counter =1). I have included screenshots of the 2 simulation cases, captured at the edge between counter = START_PULSE_2 and START_PULSE_3. There seems to be a 1 clock cycle delay that I can't explain. Is this just a reality of using tasks, or am I doing something wrong?

Here is my main code:

typedef enum {
	START_INIT,
	START_PULSE_[4] = DELAY_15ms, // power on pulse
	
	// Init commands
	START_FUNCTION_SET,
	START_ENTRY_MODE,
	START_DISPLAY_ON,
	START_CLEAR_DISPLAY,
	} lcd_ops_t;

always_ff @ (posedge clk_50M) begin
	case(counter)
		// Wait for a delay after powerup
		START_INIT: begin
			lcd_dbh <= 0;
			lcd_e <= 0;
			lcd_rs <= 0;
		end
		
		// Enable 4bit interface through 4 specific pulses
		START_PULSE_0: init_pulse('h3, INIT_PULSE, DELAY_4_1ms, task_complete, lcd_dbh, lcd_e, init_pulse_counter);
		START_PULSE_1: init_pulse('h3, INIT_PULSE, 5000, task_complete, lcd_dbh, lcd_e, init_pulse_counter);
		START_PULSE_2: init_pulse('h3, INIT_PULSE, 2000, task_complete, lcd_dbh, lcd_e, init_pulse_counter);
		START_PULSE_3: init_pulse('h2, INIT_PULSE, 2000, task_complete, lcd_dbh, lcd_e, init_pulse_counter);
		
		// Send initialization commands to LCD
		START_FUNCTION_SET: send_lcd_byte(CMD_FUNCTION_SET, 0, t

Hello!

Picture someone that does RTL coding for about 5 years in Verilog, successfully doing large designs, but has never played seriously with SystemVerilog with focus on synthesis.

When I say 'played seriously', I mean using the nice features of SystemVerilog such as Interfaces, defined data types (typedef) and (packed/unpacked) structures, Enums (mostly for FSMs) etc.

What resource (on-line, books, etc) would you recommend to quickly turn this person in SystemVerilog RTL designer ? I'd like to avoid long books like "SystemVerilog for Design 2ed" from Sutherland et al.

Thanks!

I want to be able to parse an incoming UART stream that looks something like this:

%NOTI,002A,01000000%%NOTI,002A,02000000%...etc.

Where I am interested in the 32-bit value before the ending percent sign. (it's LSB first)

ex, %NOTI,002A,<4-byteval>%

I already have a module that will take the UART stream coming in and parse it into bytes. I want to get this value, and store it in 32-bit memory location. I've got that part figured out also.

I just need a way to get only the value I need from this stream of bytes coming out of the UART receiver. The terminal shows the output strings just like that by the way, so a side question I have is: is that hex value being printed on the terminal also ascii characters? (ex. 0100 would be 0x30/0x31/0x30/0x30)? If so I will have to convert those bytes into the actual hex values first.

Does anyone have any good resources or ideas on how to do this?

Hello all!

I've seen a module which port declarations were such as:

module ss #(
        parameter WIDTH=64,
        parameter IN_NUM=8,
        parameter OUT_NUM=8
        ) (
        input wire clk,
        input wire reset,
        input [IN_NUM-1:0] i_dv,
        input [IN_NUM-1:0] [WIDTH-1:0] i_d,
        input [IN_NUM-1:0] [$clog2(OUT_NUM)-1:0] i_dd,
        output logic [OUT_NUM-1:0] [WIDTH-1:0] o_d
        );

The author said it's a verilog module, but I'm aware Verilog doesn't support that 'packed/array' kind of port declaration, and the output is a 'logic' type, which is clearly SystemVerilog. (also, $clog is a SystemVerilog system task).

I'm searching around more information about this type of port declaration. Googled around and even didn't find anything in IEEE SystemVerilog standard. Looked at IEEE-1800-2012 and IEEE-1800-2017.

Maybe I overlooked something in these huge documents. Have you guys seen something alike? Where are they documented in the standards? Any other place I can find a good info about ?

Thanks!

I'm a junior lecturer. I've prepared a set of slides, code, and designs to introduce the concept of RTL design/simulation and SystemVerilog. This is not a formal course. I assume the student has no prior knowledge.

My objectives:

1. Break the misconceptions such as "this is like programming"
2. Example centered approach. Mention little concepts (handshaking, state machines) , whenever necessary.
3. Introduce language features and design concepts via the simplest working examples.
4. Give real-world examples, but not too complicated that they miss what I'm trying to introduce.

I plan to ask them to install Vivado/Quartus beforehand and implement each example with me and test in simulation.

Examples included and their objectives

1. 1-bit full adder - idea: HDL describes a digital circuit, logical operators, wire assignment
2. N-bit full adder - module instantiation, generate loop
3. Combinational ALU using operators - arithmetic operators
4. Pipelined ALU with IPs - IP usage, show synthesis why it's better
5. Counter - sequential circuits, simplest register, always_ff
6. Parallel to Serial converter - State machine with 2 states, enums
7. Fully parallel matrix multiplier with IPs - working with multidimensional arrays

Kindly skim through the slides and let me know what you think. I'd be glad to hear where it can be improved.

View slides here - Office Online

Note: I haven't included OOP features and some advanced features like interfaces.

I made HDL Linter for Sublime Text 4

Requirements:

- Sublime Text 4 (released few days ago)

- Vivado

I tested it only on my PC, so I need someone who will check plugin on other machines. I tested it with Vivado 2019.1 and 2020.1 under Windows 10. When Vivado version will work fine then I will add linting with other software like Icarus Verilog etc.

This is one file linting so SystemVerilog require special way of writing code. You have to include all signal / variable declarations, access to global scope by $root.(*), etc.

As the title says i'd like to learn more about SV because my book of computer architecture doesn't cover much of it. Furthermore the things covered by the book are explained pretty badly.

I've seen a pdf (few pages) that quickly covers most of the synthesizable construct but i still have a lot of doubts ( The use of typedef, packages etc. )

A friend and I built a website for practicing SystemVerilog interview questions (similar to Leetcode). Our core coding and simulation features are done, and we’re working to add new questions and make the site look more professional.

Link: chipdev.io

Are there any questions you’d like to see added? Or other areas we can improve in? We’d love to get some feedback on how we can improve the site and make it better for everyone.

https://preview.redd.it/w3p7qen2kbt71.png?width=1910&format=png&auto=webp&s=7ee3360d1fb08e04e11c1193a5126cd545019934

Using basic SystemVerilog, or by UVM.

Like for learning Verilog, I've been using hdlbits (https://hdlbits.01xz.net/wiki/Main_Page). But that's for Digital Design using Verilog. Are there any similarly good websites to learn how to do Design Verification using SystemVerilog ?