I've tested it on Lattice, Altera, and Xilinx at a clock frequency of 16 MHz, 50 MHz and 100 MHZ respectively. With any where from 8-24 input channels and a memory buffer with 1024-8192 rows. It was a fun project and I learned a lot. Uses roughly 230 flip-flops. The thing I like the most is I was able to get the data sampled and saved into the buffer on very clock cycle (at the full speed of the FPGA) rather than doing it every other clock cycle or something. I didn't do any data compression nor can it do a continuous mode, in case anyone was wondering. Can work as an internal or external logic analyzer. The GUI doesn't do protocol decoding but will be something I add this summer. Enjoy!
Here is a link to the repo if you want to check it out or read the README or see a picture of the GUI.
lekgolo167/enxor-logic-analyzer: FPGA Logic Analyzer and GUI (github.com)
Basically the title,
I am a computer engineering student and I'm looking to improve myself in the acceleration field of FPGA's. I have used Vivado HLS with Zedboard until now and I want to be able to design and make accelerators using Verilog as well. I have completed a course at my university already. I feel like I lack confidence and efficiency because I'm not that familiar with the programming / design styles of bigger projects.
I already googled and found some of the GitHub repos that popup, but I wanted to ask you guys and take recommendations on which sources I could improve myself further on Verilog.
Thanks for all the help.
Edit: I felt like you guys might ask, ok so you are a beginner and what do you wanna accelerate? My work on Vivado HLS was about accelerating the multiplication of matrices (single-precision floating-point numbers) that won't fit my on-chip memory. Designing something similar with better performance is my current long term education goal.
A generic, deployable solution in order to replace a few (2-6) 74HCxx ICs.
Prefer (not critical) - qfp rather than qfn or bga, for easier working.
Prefer (not critical) NVCM for robustness/ single ic solution. 3.3V (or higher) tolerant.
Perhaps with 10-16 (or fewer) gpio that could (ideally) support a two-layer pcb fanout.
Does anything like this exist?
I was curious if there was some simple, lightweight and free tool that helps in visualising large modules quickly, just like the schematic viewer in vivado. I'm not looking for any heavy functionality but it's a pain to fire up vivado or quatrus every time I start working on a new module that I need to understand.
Has anyone done a Hardware Engineering Intern interview for Verilog, SystemVerilog, FPGA architecture, Tcl? What were some of the questions you were asked? Does anyone have any tips for my first round interview?
Some inputs and outputs are shared between the two fsm.
One approach might be similar to the way a reset wire can be used in a module.
Ie. a creset wire can be tested in the always@( posedge clk) block, to force all internal state and outputs to their reset state .
Similarly, if one had a !is_active wire, then it could be tested in the always@ block to suspend all actions.
Is this feasible? Is there a better way?
Edit,
Here's an example, and verilog complains about led having multiple drivers - even though the arbitration control should prevent that. So it looks like it's not possible/ not the right approach.
module my_fsm (
input clk,
input active ,
input wire [ 31 - 1 : 0 ] freq ,
output led
);
reg [31:0] clk_count ;
always @(posedge clk)
if(active)
begin
clk_count <= clk_count + 1;
if(clk_count > freq)
begin
clk_count <= 0;
led <= ~ led;
end
end
endmodule
module top (
input clk,
output LED_R,
input ARB,
);
wire arbitration = ARB ;
my_fsm fsm1 (
. clk(clk),
. active( arbitration) ,
. freq( 1),
. led( LED_R )
);
my_fsm fsm2 (
. clk(clk),
. active( ~ arbitration) ,
. freq( 3),
. led( LED_R )
);
endmodule
So I think the preferred approach is to mux the outputs of the two fsms. And perhaps also hold the 'unused' fsm in a state of reset, if it is desirable not to use resources.
I just added example designs to my open source Verilog UDP/IP Ethernet stack to demonstrate functionality at 25 Gbps line rate on the Alpha Data ADM-PCIE-9V3 and Xilinx VCU118 boards (both Virtex Ultrascale Plus, the design should port easily to any Virtex Ultrascale Plus board). No tricks; the whole stack runs with a 64 bit datapath in the 390.625 MHz serdes transmit clock domain, fully open source from deserializer to serializer, including UDP, IP, ARP, MAC, and PHY. Currently only closes timing on ultrascale plus parts; some more optimization will be required for operation on ultrascale parts. The changes required for 25G operation have not changed the latency at all and they have not significantly changed the utilization, so the changes will also serve to make timing closure at 10G easier. The only real difference between 10G and 25G is the GTY transceiver configuration, so it should be possible to make it runtime switchable between 10G and 25G, though I have yet to look in to that in detail.
Take a look at the code here: https://github.com/alexforencich/verilog-ethernet
Edit: The PHY portion of this code currently does not support auto negotiation, BASE-R FEC, or RS-FEC. If you need any of those features, you'll have to use some other PCS/PMA and/or MAC IP core. But the included MAC supports standard XGMII/25GMII so can be used with any 10G or 25G PCS/PMA core, and the MAC interface is AXI stream so the included MAC could be swapped out for any MAC with an AXI stream interface.
hi verilator seems the best open source verilog simulation tool. How far it is from commercial active-hdl? what thing it cant do but active-hdl can? i am going to build a risc-v core, which is a hobby project, still thinking i should buy active-hdl or not.
thanks Peter
Jonas Salk never patented the polio vaccine creating an open source for it to be affordable worldwide so polio would be eradicated. Did covid vaccine manufacturers ever offer to open source their recipes? Wouldn’t that help w/ international distribution issues? Tell me it's not for the money...
I've recently started playing with Verilog and Verilator. I think most of you around here already know about Verilator, it takes Verilog and compiles it into a cycle-accurate C++ model for simulating it. I don't have a real FPGA yet, but I wanted to somehow make the simulation interact with real hardware (LEDs, buttons and switches) until I can get my hands on an actual FPGA. So I took an STM32 board and tried compiling a Verilated blink model for it, and it works! I even tried it on a tiny 8-pin STM32G031J6. It kinda feels weird doing all of this, and it doesn't make any sense for real-world applications, but I feel like it could be quite a valuable tool for experimenting in situations where costs should be kept at an absolute minimum.
I've flared this as "Meme Friday" because I find it oddly amusing. I'm calling it FakePGA.
Good morning everyone.
For an educational project in cooperation with a supervising professor at my university, I am developping a backend simulator (linked to a React frontend webapplication) to allow students to simulate really simple and customized CPU architectures.
CPU architectures are written in Verilog. I am trying to be able to simulate those architecture REALLY fast because the webapplication has to be quite reactive and nice to use.
The main idea:
User write Assembly program for CPU on webapplication -> Assembly program is sent to backend server -> Server transform assembly program into instructions readable by CPU -> A simulator runs said CPU architecture and returns results to webapplication
As for now, we were using Chisel3 but it is not fast enough, and we are getting into more complicated designs (surch as RISC V). The webapp is slowly becoming unresponsive and unusable.
So, I am looking for a way to simulate my designs really fast, with "poking" some inputs of my CPU and "peeking" the results. Lets say I want to obtain results from simulation in under 3 to 4 seconds.
I heard about Verilator but it is quite something to learn and I am not sure if its the proper tool for my needs. I have looked into cocotb, but it does not work really well on my side. Could you guys recommend me anything ?
Thank you very much
Is it possible to have internal contention (not interfacing with the I/O blocks) on an FPGA, and if so could this damage the FPGA?
I am modeling a register file I build on a breadboard a while back. For simplicity lets say the register file has four registers all output on the same bus with some logic controlling the output enables of each of the registers. How exactly could this be done in Verilog in a way that is synthesizable. Specially, is it possible/correct to have each register share the same output bus and have them all output Z to the bus except for the one that is enabled?
I know that high impedance typically doesn't exist on an FPGA (at least internally), so is it correct to assume the synthesis tools will just conjure up some multiplexing logic to maintain proper functionality?
Hi all, I'm an international student that had to do the fall quarter remotely due to visa issues. I was supposed to arrive on campus for the first time on the 1st of Janurary. This is reflected in my I-20 which lists the 3rd of Janurary as my start date.
I would like to arrive on campus on the 20th of Janurary but I require a new I-20 to do so because entrance to the states after the listed I-20 start date is not guaranteed by the CBP.
The problem is that the OIA took more than 3 weeks to process my previous application for a new I-20 with a deferred start date. So, I'm worried that if I request for a new I-20 after the OIA reopens, I would not be issued a new I-20 by the 20th of Janurary.
Do any of you know who I should contact about this? I'm kinda worried about it and would not like to risk missing another quarter. Alternatively, should I just apply for early arrival through the housing portal and arrive on the 3rd of Janurary?
Please suggest films where the lone hero 'out smarts' the system for revenge.
Beginner here😅.
Can someone please explain how do I add delay to my synthesized program in Verilog because the # function cannot be synthesized. I looked up on the internet and found people suggesting to use counters and clocks but couldn't really grasp hold of it. Any help would be appreciated.
(I'm trying to get one of my interfaced peripherals to start after a delay of 3 seconds)
Does anyone know of a good open source program for formatting coding style in Verilog? Like clang for c++. I couldn't find any good equivalents for Verilog but thought there must be something out there.
I’ve recently started a new blog series: Maths and Algorithms with FPGAs.
The first part is Numbers in Verilog.
It examines how integers are represented and digs into the challenges of signed numbers in Verilog. I’ve tried to balance rigour with simplicity. Do let me know if you have any suggestions or corrections.
I'm looking for suggestions on what to do next? What I've covered so far is some projects and systems with FSM and decent test benches.
I think reading an advanced book about design would help me a lot; in which the author would probably discuss certain design issues and scalability etc and its Verilog code. Most of the books I've found cover the same basics and I think I'm no longer a beginner. Do you have any suggestions on that?
or Should I learn SystemVerilog as a progression to Verilog?
Also, I've read this q&a on SE about design patterns or "models of good practices" in HW design, but it's 10 years old, what should I look into? https://electronics.stackexchange.com/questions/14133/is-there-a-design-patterns-for-synthesizable-rtl
Or should I learn & do advanced projects to get to an intermediate or advanced level? please suggest some, the type that forces me to think about better design.
This question might be repeated as I feel it's somewhat generic; please, feel free to throw in some links, that'd be much appreciated. I'll read them.
Thank you
