Zen (microarchitecture) Puns

I'm planning my first pc build and iv hit a bit of roadblock. The motherboard I was planning on getting says it takes in zen2 but any cpu in my buget is zen+. Normally I would just settle for a ryzen 3 instead of 5 with zen 2 Wich is in my buget.

My father (who is financing 40 precent of the biuld) says we can't go for anything lower than icore or ryzen 5. I'm honestly not sure how different ryzen 3 and 5 are.

They are certenantly both powerfully enough for me to play minecraft and cod.

What can I do? Should I just get a more cheap mother board to fit a zen+ and throw more cash in the processor or should I convince my father?

Funny story actually my father has a laptop where he plays old ass games and it take a long time to open any games. He is convince it's because his laptop has an ryzen 3(not sure Wich one exactly) in it. Meanwhile he is getting upoards of 170 fps on older games. I told him it the fact that it has an hard drive instead of ssd but he didn't belive me

Tldr: can a motherboard with zen 2 microarchitecture take in zen+ CPUs?

Running Ubuntu/Linux, I have two computational tasks, a matlab one, and a povray one. I have two Threadrippers, the 2950X with 16/32 cores/threads and 2990WX with 32/64.

Both tasks are small memory footprint (~1GB, the machines have 128GB) "number crunchers", there are no I/O issues to consider.

For the matlab task, I get the best performance by using CORES amount of threads (or --singleCompThread tasks) on the CPU; this is what matlab decides on by default (ie. a task using matlab’s multithreading settles on CORES*100% cpu usage).

For the povray task, I get the best performance by using THREADS amount of threads on the CPU. The CPU settles on THREADS*100% cpu usage. This is also what the program decides on by default.

For the matlab task, the performance ratio (yield) between chips is 1:1 — the chips perform ~equally. For the povray task, the performance ratio is 1:2 — the 32 core chip is ~twice as fast as 16 core (as could be expected).

I haven't verified with zenmonitor yet, but there should be no boosting/throttling/(air-)cooling issues involved, ie. the chips "can" run at their highest boost for an extended period without apparent issues.

I've read the wiki description, but I don't spot an obvious explanation for the "discrepancy". What could be going on here?

Matlab version for these has been 2018b; POV-Ray is v3.7 stock from ubuntu.

Edit: details

As I could read on anandtech side, Zen2 has the best ratio to Memory/IF(1:1) ratio about 3733 GHz. After that you have to go 2: 1 ratio. But could AMD have made it possible to go for 1.5 or even better, 1.0 / 1.25 / 1.5 / 1.75 / 2 ratio, thereby utilizing better and higher memory speed?

Hello, I am currently working on a design for a custom microarchitecture based on RISCV, and was hoping for some suggestions for articles related to design methodology. Now I mean as in a process going from: design of functionality -> design of HDL -> testing. Are there any good articles you would recommend that specify some good approaches to designing a custom microarchitecture?

Hi everyone! My old ThinkPad died, and while I hope to get it repaired in the future, I'll be upgrading to a new laptop in the interm (especially since I'm overdue for one anyway). I want to migrate my Gentoo installation from the ThinkPad, but the issue is that my ThinkPad used an AMD FX chip, while the Framework I'm replacing it with uses an Intel Tiger Lake chip. The advice I've found recommends recompiling @system with the old processor to generic or something like core2, that both processors will understand, but I can't do that since the old laptop is out of commission. And while I haven't tried it yet since I don't physically have the new laptop, I'm 85% sure I won't be able to run the old kernel and gcc because it doesn't support FMA4 or the XOP sets, and if gcc ever decided to insert even a single instruction using these, I'll just get a kernel panic.

I thought of maybe chrooting from another distro off a USB stick and using its compiler, but I'm not sure how I could get portage to use the host's toolchain from inside the chroot. I also considered extracting a stage3 from /, but I'm worried it would overwrite not only the old toolchain but also some of my other files, like config files and the like. Is there a way to upgrade in this situation, without doing a full reinstall?

I may be wrong so please correct me but as far as I know the new Ryzen 4000 APUs (mobile and desktop) are still on Zen 2 while the regular CPUs will be Zen 3, is there any real reason for this? Just curious whether it's just a marketing thing

Hi all

I'm a CS student and I have to do a project changing the microarchitecture of a processor, my task will be to change whatever it uses to connect the internal components (ifu, alu, etc) to use a NoC (Network on a Chip).

What processors have good documentation or are easy to dwell into? I'd prefer using Verilog or VHDL, but I don't mind learning something new. What ohter things should I have in mind before starting?

Good intel.

Hi!

Before stating my question here is some context: I am looking forward to develop a RV32I core as a case study for learning the tools and processes that are used on the semiconductor industry. My idea is to develop it as a side project until I finish my studies and use it as an item on my resumé. I am aware that many RISC-V cores are available on the web and mine would make no difference to the community, but it would be a tremendous source of expirience for me.

My idea on the core development is to define an specification (clock and power initially), develop a high-level model of the core (golden) and then dive into the Verilog description, test it using some broadly accepted methodologies and, deploy it to a FPGA and run the on-board tests. I am currently on the high-level model of the core where my question arised.

Is there any way to high-level model a microarchitecture? maybe something that allows one to try diffent microachitectures and get some data on which has the greater performance and/or uses the less power. I am asking this because I don't want to stick to the first microarchitecture that comes into my mind. I am afraid of answering "just because" when, hopefully, an interviewer asks me why did I put the decoder on the second stage and not in the first one.

I have been researching on that topic for the last days and I found that SystemC might be the right choice for it. I am also thinking about Chisel since it could probably save me from the Verilog coding. But I don't know if those are the right tools for the task and/or if they are worth the time since I have not found information about those tools being used on the industry.

Thanks in advance for any reply!

N.

P.D. This is my first post so any feedback on the posting itself would be also appreciated.

AMD publishes EDAC driver for Family 19h Models 10h-1Fh and A0h-AFh CPUs.

AMD has published a set of patches for the company's EDAC (Error Detection and Correction) driver code for the next-generation EPYC processors based on the Zen 4 microarchitecture. The new patches indicate that the upcoming CPUs will support unprecedented memory bandwidth and capacity per socket.

The patches (found by Phoronix) bring in support for DDR5 registered DIMMs (RDIMMs) and DDR5 load-reduced DIMMs (LRDIMMs) for the fourth-generation EPYC processors codenamed Genoa (Family 19h Models 10h-1Fh and A0h-AFh CPUs).

The patches also confirm that the upcoming EPYC 7004-series will support up to 12 memory controllers per socket, up from eight for AMD's existing server parts. Unfortunately, we do not know how many DIMMs per channel (DPC) the chips will support.

Twelve 64-bit DDR5 memory channels would theoretically increase the memory bandwidth available to Genoa processors to a whopping 460.8 GB/s per socket, a significant increase compared to the 204.8 GB/s available to current-generation EPYC CPUs with DDR4-3200.

Memory bandwidth alone will not be the only improvement on next-generation EPYC 'Genoa' CPUs. Twelve memory channels will also enable higher memory capacities for the new processors. Samsung has already demonstrated 512GB DDR5 RDIMMs and confirmed that 768GB DDR5 RDIMMs were possible. Even using 12 512GB modules, AMD's next-generation server processors could support up to 6TB of memory (up from 4TB)

However, if Genoa supports two RDIMMs per channel, that capacity will stretch up to 12TB of DDR5. AMD could increase the capacity per memory channel and per socket further With LRDIMMs (due to octal-ranked module architecture), albeit at the cost of performance.

AMD's EPYC 7004-series 'Genoa' processors will bring tangible memory improvements compared to existing server processors, which will naturally improve their real-world performance

link

I have an old AMD Duron CPU that I would like to try my hand at Lapping the die so that I could see the parts of the microarchitecture like it was on a wafer. Now I have no experience with die Lapping and I'm not sure where to find information about it as most people die lap to decrease thermals. I would appreciate any help/resources I could use to find out more. Also the CPU has no IHS.